Abstract:This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset C… Show more
“…Several high-performance current measurement circuit topologies are discussed in [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]. One of the common architectures for low current measurements is based on an integrator followed by a differentiator [34][35][36].…”
Section: Design Of Readout Circuitmentioning
confidence: 99%
“…Furthermore, it is accompanied by a significant temperature sensitivity and nonlinearity that are difficult to address without the use of an additional temperature compensation circuit. Few other current measurement circuits rely on capacitive TIA (C-TIA) to perform current-to-frequency (I-F) conversion [33]; timed integrators with a switched capacitor network or correlated double sampler [37][38][39][40][41]; variable gain amplifiers with external voltage control or digital gain control [26,31,32]; and use of large feedback resistor realized as an on-chip active pseudo resistor or off-chip external resistor. In the case where a pseudo resistor is realized using a transistor, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth that is undesirable.…”
The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Amplifier (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor (Rf) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µA–100 µA. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational amplifier (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications.
“…Several high-performance current measurement circuit topologies are discussed in [26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41]. One of the common architectures for low current measurements is based on an integrator followed by a differentiator [34][35][36].…”
Section: Design Of Readout Circuitmentioning
confidence: 99%
“…Furthermore, it is accompanied by a significant temperature sensitivity and nonlinearity that are difficult to address without the use of an additional temperature compensation circuit. Few other current measurement circuits rely on capacitive TIA (C-TIA) to perform current-to-frequency (I-F) conversion [33]; timed integrators with a switched capacitor network or correlated double sampler [37][38][39][40][41]; variable gain amplifiers with external voltage control or digital gain control [26,31,32]; and use of large feedback resistor realized as an on-chip active pseudo resistor or off-chip external resistor. In the case where a pseudo resistor is realized using a transistor, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth that is undesirable.…”
The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Amplifier (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor (Rf) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µA–100 µA. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational amplifier (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications.
“…Reference voltage generators are required to stabilize the overall PVT variation, and also need to be implemented without modifying the fabrication process [ 21 , 22 , 23 ]. The bandgap reference voltage generator (BGR) is a popular reference voltage generator that successfully achieves the requirements [ 24 , 25 ]. Low power and low voltage operation are the characteristics of reference voltage generators.…”
A proposed prototype of a 10-bit 1 MS/s single-ended asynchronous Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with an on-chip bandgap reference voltage generator is fabricated with 130 nm technology. To optimize the power consumption, static, and dynamic performance, several techniques have been proposed. A dual-path bootstrap switch was proposed to increase the linearity sampling. The Voltage Common Mode (VCM)-based Capacitive Digital-to-Analog Converter (CDAC) switching technique was implemented for the CDAC part to alleviate the switching energy problem of the capacitive DAC. The proposed architecture of the two-stage dynamic latch comparator provides high speed and low power consumption. Moreover, to achieve faster bit conversion with an efficient time sequence, asynchronous SAR logic with an internally generated clock is implemented, which avoids the requirement of a high-frequency external clock, as all conversions are carried out in a single clock cycle. The proposed error amplifier-based bandgap reference voltage generator provides a stable reference voltage to the ADC for practical implementation. The measurement results of the proposed SAR ADC, including an on-chip bandgap reference voltage generator, show an Effective Number of Bits (ENOB) of 9.49 bits and Signal-to-Noise and Distortion Ratio (SNDR) of 58.88 dB with 1.2 V of power supply while operating with a sampling rate of 1 MS/s.
“…The required VCM of 2.5 V (VDD/2) is provided by VCM Gen. To digitalize the input analog BPSK signal through the proposed DBPSK demodulator, the amplified input analog signal and its invert are required. The STOD circuit converts the single input analog signal to the required differential signal [ 9 ]. Through the SPI, a graphic user interface (GUI) programmer on a computer controls the RX’s digital controller.…”
Section: Overall Architecture and Building Blocksmentioning
This paper presents an on-chip fully integrated analog front-end (AFE) with a non-coherent digital binary phase-shift keying (DBPSK) demodulator suitable for short-range magnetic field wireless communication applications. The proposed non-coherent DBPSK demodulator is designed based on using comparators to digitize the received differential analog BPSK signal. The DBPSK demodulator does not need any phase-lock loop (PLL) to detect the data and recover the clock. Moreover, the proposed demodulator provides the detected data and the recovered clock simultaneously. Even though previous studies have offered the basic structure of the AFEs, this work tries to amplify and generate the required differential BPSK signal without missing data and clock throughout the AFE, while a low voltage level signal is received at the input of the AFE. A DC-offset cancellation (DCOC), a cascaded variable gain amplifier (VGA), and a single-to-differential (STOD) converter are employed to construct the implemented AFE. The simulation results indicate that the AFE provides a dynamic range of 0 dB to 40 dB power gain with 2 dB resolution. Measurement results show the minimum detectable voltage at the input of AFE is obtained at 20 mV peak-to-peak. The AFE and the proposed DBSPK demodulator are analyzed and fabricated in a 130 nm Bipolar-CMOS-DMOS (BCD) technology to recover the maximum data rate of 32 kbps where the carrier frequency is 128 kHz. The implemented DCOC, cascaded VGA, STOD, and the demodulator occupy 0.15 mm2, 0.063 mm2, 0.045 mm2, and 0.03 mm2 of area, respectively. The AFE and the demodulator consume 2.9 mA and 0.15 mA of current from an external 5 V power supply, respectively.
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