A 72 Mb/s PRML disk-drive channel chip with an analog sampled-data signal processor

Abstract

A high performance, 72Mb/s PRML readwrite channel chip has read path adaptive equalization, Viterbi metric calculation, and timing recovery functions accomplished with an analog sampled-data processor (SDP). The lpm BiCMOS chip nominally operates a t lOOMWs (112MSh) over a 0°C to 70°C temperature and +lo% supply voltage range. It nominally dissipates less than 80OmW from 5V a t 1OOMWs.Partial-response (PR) signaling with maximum-likelihood sequence (ML) detection produces superior performance compared to previously-used analog peak detection in magnetic rigid disk drive recording channels. To the present day, the reported class IVPRMLchannel chips have beenimplemented with digital signal processing [l, 21. In Class IV PRML, the serial read data stream can be processed as two interleaved data streams. This halves the data rate and simplifies the Viterbi detector. The simplicity allows signal processing with continuous-time analog and analog sampled-data processing.The simplified chip block diagram is shown in Figure 1. It includes an automatic gain control (AGC), programmable continuous-time 7-pole filter with programmable 2-zero boost, three-tap adaptive equalizer, Viterbi detector, servo data pulse detector and servo demodulator, timing-recovery phase lock loop (PLL), 8,9-code encodeddecoder (ENDEC), time-base generator, serial port with control data storage, and write precompensation.The AGC accepts signal levels from 2OmVpp to 250mVpp and operates in two modes. At the start of read mode, a synchronization pattern is read to acquire the sample data timing. During this time, AGC operates on the continuous-time signal peaks. Once timing synchronization is acquired, AGC is switched to operate on the sampled data because the data "1" samples may or may not occur a t the continuous-time signal peak.The programmable filter and time base generator support constant-density recording where the data rate varies with the disk data-track radius. Coarse equalization is provided by a programmable 7-pole 0.05" equal-ripple analog filter with two programmable real-axis zeros providing up to 13db boost [3].The analog sampled data processing is accomplished with interleaved track and hold circuits (T). The structure is similar to that described in Reference 4, with the track and hold sampling periods equal to the code rate period. The adaptive equalizer interleaving structure is shown in Figure 2. Alternate Ts are sampled with A and B clocks. One half of a trackand-hold circuit is shown in Figure 3. Two track-and-hold halves are used to form a pseudo-differential circuit. Differential signal processingmaximizes speed while minimizingnoisecoupling problems. At high sample rates and 50% duty cycle operation, differential hold droop is not a problem. The trackand-hold uses a bipolar transistor switch to allow a differential low-level gate signal and a low-offset voltage bipolar buffer.The ada ptive three-tap transversal equalizer further equalizes the signal to the PR4 target response and automatically adjusts for the effects of re...

A parallel architecture for multilevel decision feedback equalization

“…Class IV partial response equalization followed by a maximum likelihood detector (PR4ML) has successfully replaced peak detectors in many current hard disk drive products [4], [5], [17]. In a linear channel dominated by additive white Gaussian noise, PR4ML clearly outperforms peak detection.…”

“…Moreover, this forward filter requires no high-frequency boost nor does it have strict requirements on its phase response. In contrast, the forward filter in PR4ML channels incorporates an equalripple filter with 9 to 12 dB of high-frequency boost [5]. With high-frequency boost, the 3 dB cutoff of the forward filter in PR4ML channels is in the vicinity of 0.5 .…”

Practical MTR-FDTS (τ=2) read channel for the <200 Mbit/sec Era

“…Class IV partial response equalization followed by a maximum likelihood detector (PR4M.L) has largely supplanted peak detectors in read channels for hard disk drives [1] [2]. PR4h4L generally performs well for user bit densities in the range of 2.0-2.2 PW50, where PW50 refers to the half height width of a transition [3].…”

IoT receiver techniques: on filtering, power consumption and phase noise

“…Several approaches still used the direct implementation architecture (Fig. 2.1a) [40][41][42][43][44][45][46][47][48][49][50][51] -where the delay line is implemented using switch-capacitor amplifiers [52] -similar to the charge transfer device analog FIR 2.3. Analog FIR Filters Prior Art Figure 2.9: Analog FIR filter with sub-sampled output as pre-filter of a SAR ADC [68].…”

“…Analog FIR techniques can also be implemented as equalizers [45-48, 57, 59-62, 117]. In the 1990s, the analog FIR equalizer was a popular research topic for the read-out circuits of magnetic storage devices [45,46,48,[57][58][59][60][61][62].…”