A 700MHz to 2.5GHz Cascode GaAs Power Amplifier for Multi-Band Pico-Cell Achieving 20dB Gain, 40dBm to 45dBm OIP3 and 66% Peak PAE

Nitesh, Ram Sharma; Rajendran, Jagadheswaran; Ramiah, Harikrishnan; Manaf, Asrulnizam Abd

doi:10.1109/access.2017.2776143

Cited by 24 publications

(3 citation statements)

References 43 publications

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“…Phase difference of 3° is observed up to the 21.8 dB Pout with bias combination of VB1 = 0.9 V, VB2 = 1.0 V and VB3 = 0.6 V 921 MHz. According to [49], a deviation of more than 5° in AM-PM response is equivalent to the 1-dB gain compression in AM-AM response.…”

Section: Measurement Resultsmentioning

confidence: 99%

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

Rawat

Rajendran

Mariappan³

et al. 2022

IEEE Access

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This paper presents a bias modulation linearization technique for a 919-923 MHz CMOS power amplifier which employs driver voltage modulation and main amplifier split bias. Through the proposed linearization technique, it is observed that the peak third-order intercept point (OIP3) across the output power is shifting according to the bias conditions of the split-bias power amplifier (SBPA). The third-order transconductance (gm3) terms are suppressed at the output by phase cancellation achieved by optimization of the bias voltages of the PA. A high dynamic range bias circuit is integrated at the driver and split main to enhance the linearity of the CMOS PA, eradicating the need for pre-distortion linearizers. The two-stage SBPA is designed and fabricated in a 180 nm CMOS process with six-metal layers and a chip size of 1.820 x 1.771 mm 2 to operate at the supply voltage of 3.3 V. The bias voltages of both driver and split main stages are varied from 0 V to 2.0 V with a linear step size of 0.2 V. The proposed SBPA delivers a saturated output power (Pout) of 27 dBm with maximum power-added efficiency (PAE) of 44.4 % and peak OIP3 of 39 dBm. A maximum linear Pout of 21 dBm with 29 % PAE is achieved at an adjacent channel leakage ratio (ACLR) of -30 dBc and 4 % error vector magnitude (EVM), satisfying the LoRa specifications.INDEX TERMS Adjacent channel leakage ratio (ACLR), bias circuit, complementary metal-oxidesemiconductor (CMOS), error vector magnitude (EVM), intermodulation distortion (IMD), long-range (LoRa), power amplifier, radio frequency power amplifier (RFPA), third-order intercept point (OIP3)

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Section: Measurement Resultsmentioning

confidence: 99%

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

Rawat

Rajendran

Mariappan³

et al. 2022

IEEE Access

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“…Deviations by 4° in AM-PM are achieved up to 27.6 and 27.3 dBm at 2.45 and 2.7 GHz, respectively. An AM-PM deviation by 5° or more is approximately equivalent to a gain compression of 1 dB or more [ 26 ]. The AM-PM flatness achieved indicates the linearization mechanism using DAWPD is effective.…”

Section: Operation Principlementioning

confidence: 99%

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

et al. 2023

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This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design’s robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

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“…GaAs substrates have become the second most important semiconductor materials owing to their high saturated electron drift velocity, low field mobility, low parasitics, and good interdevice isolation. Thus, they can be employed in various systems, including medical treatment, information storage, communications, military application, lasing, and sensing [13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

Fabrication of QFN-Packaged Miniaturized GaAs-Based Bandpass Filter with Intertwined Inductors and Dendritic Capacitor

et al. 2020

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This article presents a compact quad flat no-lead (QFN)-packaged second-order bandpass filter (BPF) with intertwined inductors, a dendritic capacitor, and four air-bridge structures, which was fabricated on a gallium arsenide (GaAs) substrate by integrated passive device (IPD) technology. Air-bridge structures were introduced into an approximate octagonal outer metal track to provide a miniaturized chip size of 0.021 × 0.021 λ0 (0.8 × 0.8 mm2) for the BPF. The QFN-packaged GaAs-based bandpass filter was used to protect the device from moisture and achieve good thermal and electrical performances. An equivalent circuit was modeled to analyze the BPF. A description of the manufacturing process is presented to elucidate the physical structure of the IPD-based BPF. Measurements were performed on the proposed single band BPF using a center frequency of 2.21 GHz (return loss of 26.45 dB) and a 3-dB fractional bandwidth (FBW) of 71.94% (insertion loss of 0.38 dB). The transmission zero is located at the 6.38 GHz with a restraint of 30.55 dB. The manufactured IPD-based BPF can play an excellent role in various S-band applications, such as a repeater, satellite communication, and radar, owing to its miniaturized chip size and high performance.

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A 700MHz to 2.5GHz Cascode GaAs Power Amplifier for Multi-Band Pico-Cell Achieving 20dB Gain, 40dBm to 45dBm OIP3 and 66% Peak PAE

Cited by 24 publications

References 43 publications

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

A 919 MHz—923 MHz, 21 dBm CMOS Power Amplifier With Bias Modulation Linearization Technique Achieving PAE of 29% for LoRa Application

A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

Fabrication of QFN-Packaged Miniaturized GaAs-Based Bandpass Filter with Intertwined Inductors and Dendritic Capacitor

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