A Wide-Bandwidth PVT-Reconfigurable CMOS Power Amplifier with an Integrated Tunable-Output Impedance Matching Network

Abstract

This paper proposes a wideband CMOS power amplifier (PA) with integrated digitally assisted wideband pre-distorter (DAWPD) and a transformer-integrated tunable-output impedance matching network. As a continuation of our previous research, which focused only on linearization tuning for wideband and PVT, this work emphasized improving the maximum output power, gain and PAE across the PVT variations while maintaining the linearity for a wide frequency bandwidth of 1 GHz. The DAWPD is employed at the driver stage to realize a pre-distorting characteristic for wideband linearization. The addition of the tunable-output impedance matching technique in this work provides stable output power, PAE and gain across the PVT variations, through which it improves the design’s robustness, reliability and production yield. Fabricated in CMOS 130 nm with an 8-metal-layer process, the DAWPD-PA with tunable-output impedance matching can achieve an operating frequency bandwidth of 1 GHz from 1.7 to 2.7 GHz. The DAWPD-PA attained a maximum output power of 27 to 28 dBm with a peak PAE of 38.8 to 41.3%. The power gain achieved was 26.9 to 29.7 dB across the targeted frequencies. In addition, when measured with a 20 MHz LTE modulated signal, the DAWPD-PA achieved a linear output power and PAE of 24.0 to 25.1 dBm and 34.5 to 38.8% across the frequency, respectively. On top of that, in this study, the DAWPD-PA is proven to be resilient to process-voltage-temperature (PVT) variations, where it achieves stable performances via the utilization of the proposed tuning mechanisms, mainly contributed by the proposed transformer-integrated tunable-output impedance matching network.

A State-of-the-Art Review on CMOS Radio Frequency Power Amplifiers for Wireless Communication Systems

“…Based on the aforementioned design, S. Mariappan et al (2023) further improved the presented design by proposing a reconfigurable CMOS PA with digital linearizers and a tunable-output impedance matching network for PVT robustness [ 136 ]. The digital linearizer was implemented at the driver stage of the CMOS PA, which acted as the wideband pre-distorter.…”

“… Linear PAE across linear output power for the proposed linearity enhancement techniques [ 116 , 118 , 119 , 121 , 123 , 124 , 129 , 132 , 133 , 134 , 135 , 136 , 137 , 142 , 143 , 144 , 145 , 146 , 147 , 148 , 149 , 150 ]. …”

“…Figure 25. Linear PAE across linear output power for the proposed linearity enhancement techniques[116,118,119,121,123,124,129,[132][133][134][135][136][137][142][143][144][145][146][147][148][149][150].…”