A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Qiao, Ming; Li, Yanfei; Zhou, Xin; Li, Zhaoji; Zhang, Bo

doi:10.1109/led.2014.2326185

Cited by 61 publications

(18 citation statements)

References 11 publications

(12 reference statements)

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“…where RD and RB are the resistance of the N-pillar and N-buffer layer respectively, RPC the resistance of the planar channel and RTC the resistance of the trench channel. In this paper, to illustrate the credibility of the simulation, the TCAD simulation [26] is calibrated to experimental breakdown characteristics (Ids-Vds) data extracted from N-Buffer SJ-LDMOS [8] and Triple RESURF (Reduced SURface Field) LDMOS [27] with a certain channel width (WCh) shown in Fig. 2 (a).…”

Section: Device Structure and Working Principlementioning

confidence: 99%

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Cao

Jiao

2020

IEEE J. Electron Devices Soc.

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In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (RON,sp) of 28.53 mΩ• cm 2 , which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV 2 /RON,sp of DG SJ-LDMOS is increased by 85.5 %.

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Section: Device Structure and Working Principlementioning

confidence: 99%

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Cao

Jiao

2020

IEEE J. Electron Devices Soc.

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“…However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly. Furthermore, even though device miniaturization is crucial for all voltage ranges, in the past few decades, most studies have been done on large LDMOS devices for mid-voltage and high-voltage applications [15][16][17][18][19][20][21][22][23][24][25][26][27]. And unfortunately, a thorough study on scaling of the planar LDMOS technology, limited to a straightforward planar device design, has not yet been performed.…”

Section: Introductionmentioning

confidence: 99%

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Saadat

Put

Edwards

et al. 2020

IEEE J. Electron Devices Soc.

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We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a predetermined leakage current suitable for lowvoltage power applications (3.3V and 5V). For devices with a channel length exceeding 40 nm, reducing the channel length decreases the onresistance as expected. Below 40 nm, an increase in resistance is observed as the result of an increased body doping concentration leading to significant electron mobility degradation in the channel area.

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“…High-voltage Lateral Diffused Metal Oxide Semiconductor Transistor (LDMOS) is very suitable for the applications of Smart Power Integrated Circuit [1,2,3,4,5,6,7,8]. Usually, p-channel LDMOS (pLDMOS) is very attractive in the full complementary high-voltage driver ICs [9,10,11,12,13,14].…”

Section: Introductionmentioning

confidence: 99%

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

Peng

Zhao

et al. 2020

IEICE Electron. Express

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In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer, which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance (R on,sp) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the R on,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the R on,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.

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A 700- V Junction-Isolated Triple RESURF LDMOS With N-Type Top Layer

Cited by 61 publications

References 11 publications

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

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