A 6ns 4Kb bipolar RAM using switched load resistor memory cell

et al. 1987

For speed‐up technologies for bipolar RAMs, an on‐chip address latch function, a new sense circuit using a dummy cell, a Darlington wordline driver, etc., have been reported. However, their effects still have not been clarified. According to the quantitative evaluation of the forementioned circuit technologies, with respect to the speed‐improvement and stable operation of memory cells in this paper, the speed can be improved by 30 percent and no instability of data retention occurs in memory cells even using the Darlington wordline driver. The 4‐Kbit RAM has been fabricated with the forementioned circuit technologies and the 1.5‐μm U‐groove isolation process. The high speed of the mentioned circuits and the stable operation of memory cells have been confirmed by evaluation using the EB tester. The performances obtained are access time of 3.5 ns (by using an on‐chip address latch function, it can be improved to 2.5 ns from the viewpoint of the system) chip area of 12.7 mm2, and power dissipation of 1 W.

4–kbit bipolar RAM with on–chip address latch function

Nambu

Kanetani

et al. 1987

Study on discharge circuits for word‐lines in high‐speed bipolar rams

Homma

Sakurai

1991

To speed‐up the access of bipolar RAMs, the fall‐time of the word‐line drive voltage must be reduced by the discharge circuit. Various word‐line discharge circuits have been proposed for this purpose. This paper aims at the determination of the best discharge circuit for the future high‐speed, large‐capacity RAM. Four typical conventional kinds of discharge circuits plus one each newly proposed discharge circuit for small and large capacities are applied to the same memory cell array, and the performances are compared by circuit simulation with the same load condition and the same device. As a result, when the degree of integration is not very high and the voltage drop in the word‐line can be ignored, the conventional delayed‐type discharge circuit is the best. When the integration is high and the voltage‐drop in the word‐line cannot be ignored, the newly proposed discharge circuit flowing the discharge current also from the upper word‐line is shown to be the best. Thus, it is concluded that the newly proposed discharge circuit is well‐suited to the future high‐speed, large‐capacity RAMs. The performance of the typical delayed‐type discharge circuit is actually measured for 4‐kbit RAM; and it is verified that the fall‐time of the word‐line drive voltage is reduced, as in the result of simulation. This paper presents a discussion concerning primarily the comparison of performances among the newly proposed and conventional discharge circuits.

Characteristics of high‐speed bipolar RAMs under address‐skew condition

Homma

1992

This paper considers a high‐speed bipolar RAM with the integration density of 4 kb, as an example. The access time and the operational margin are examined by simulation and actual measurement in representing the effect of the timing difference between address input signals (called skew) on the characteristics of the memory. First, it is shown that the access time increases by approximately 0.9 ns (17 percent) by the skew. This is due to the operation of the sense amplifier producing the differential output. As a result of the skew, the switching of the sensing current is delayed and the period is produced in which the differential sense outputs are kept at the same potential. This equipotential period lasts longer due to the skew than in the case without a skew, which produces a waveform distortion in the data output signal. This waveform distortion increases the access time. However, the increase is suppressed by optimizing the timing design of the internal circuit. Next, the memory cell potential in the transient state is considered and the relation between the skew and the operational margin is examined. It is shown as a result that when a skew exists, the circuit experiences a special transient state which is not observed when there is no skew. It is shown that the operational margin in this state is determined by the particular memory, cell with a large variation in the forward voltage VF of Schottky Barrier Diode (SBD). It has been proven useful to reduce the variation of VF and to increase the SBD capacitance to reduce the dependency on the skew. Finally, the relation between the two forementioned skew dependencies and the internal address latch function is discussed.