Study on discharge circuits for word‐lines in high‐speed bipolar rams

Abstract

To speed‐up the access of bipolar RAMs, the fall‐time of the word‐line drive voltage must be reduced by the discharge circuit. Various word‐line discharge circuits have been proposed for this purpose. This paper aims at the determination of the best discharge circuit for the future high‐speed, large‐capacity RAM. Four typical conventional kinds of discharge circuits plus one each newly proposed discharge circuit for small and large capacities are applied to the same memory cell array, and the performances are compared by circuit simulation with the same load condition and the same device. As a result, when the degree of integration is not very high and the voltage drop in the word‐line can be ignored, the conventional delayed‐type discharge circuit is the best. When the integration is high and the voltage‐drop in the word‐line cannot be ignored, the newly proposed discharge circuit flowing the discharge current also from the upper word‐line is shown to be the best. Thus, it is concluded that the newly proposed discharge circuit is well‐suited to the future high‐speed, large‐capacity RAMs. The performance of the typical delayed‐type discharge circuit is actually measured for 4‐kbit RAM; and it is verified that the fall‐time of the word‐line drive voltage is reduced, as in the result of simulation. This paper presents a discussion concerning primarily the comparison of performances among the newly proposed and conventional discharge circuits.