4–kbit bipolar RAM with on–chip address latch function

Abstract

For speed‐up technologies for bipolar RAMs, an on‐chip address latch function, a new sense circuit using a dummy cell, a Darlington wordline driver, etc., have been reported. However, their effects still have not been clarified. According to the quantitative evaluation of the forementioned circuit technologies, with respect to the speed‐improvement and stable operation of memory cells in this paper, the speed can be improved by 30 percent and no instability of data retention occurs in memory cells even using the Darlington wordline driver. The 4‐Kbit RAM has been fabricated with the forementioned circuit technologies and the 1.5‐μm U‐groove isolation process. The high speed of the mentioned circuits and the stable operation of memory cells have been confirmed by evaluation using the EB tester. The performances obtained are access time of 3.5 ns (by using an on‐chip address latch function, it can be improved to 2.5 ns from the viewpoint of the system) chip area of 12.7 mm2, and power dissipation of 1 W.