A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder

Blanksby, Andrew; Howland, C.

doi:10.1109/4.987093

Cited by 475 publications

(306 citation statements)

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“…While fully-parallel LDPC decoder designs [6] suffered from complex interconnect issues, various semi-parallel implementations based on structured LDPC codes [2], [7]- [9], [13]- [14] alleviate the interconnect complexity. All the structured LDPC codes share the property that the H matrix is constructed out of cyclic shifted version of identity matrix and null matrices.…”

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confidence: 99%

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

Gunnam

Choi

Yeary

et al. 2007

2007 IEEE International Conference on Communications

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Abstract-We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2x when compared to the recent state-of-the-art decoder architectures.Index Terms-low-density parity-check (LDPC) codes, offset min-sum, on-the-fly computation, decoder architecture, layered decoding, turbo-decoding message passing, irregular LDPC,IEEE 802.16e.

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confidence: 99%

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

Gunnam

Choi

Yeary

et al. 2007

2007 IEEE International Conference on Communications

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“…Both these computations have high complexity, and need to be implemented using parallel hardware to achieve the desired performance requirements. The results of the parallel hardware units need to be communicated with other units, which yields the traffic matrices; communication is known to be a bottleneck for both FFT [7] and LDPC [1].…”

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confidence: 99%

Scheduling Traffic Matrices On General Switch Fabrics

Prakash

Mohiyuddin

et al.

14th IEEE Symposium on High-Performance Interconnects (HOTI'06)

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Section: Introductionmentioning

confidence: 99%

“…Such fully parallel decoder could achieve extremely high decoding speed, e.g., a 1024-bit, rate-1/2 LDPC code fully parallel decoder [4] with the maximum symbol throughput of 1 Gbit/s has been implemented using ASIC technology. However, the primary disadvantage of fully parallel design is that with the increase of code length the hardware complexity will become more and more prohibitive for many practical purposes, e.g., the ASIC LDPC decoder [4] with only 1K-bit code length consumes 1.7M gates. Moreover, as pointed out in [4], the routing overhead is quite formidable due to the large code length and randomness of the Tanner graph.…”

Section: Introductionmentioning

confidence: 99%

“…However, the primary disadvantage of fully parallel design is that with the increase of code length the hardware complexity will become more and more prohibitive for many practical purposes, e.g., the ASIC LDPC decoder [4] with only 1K-bit code length consumes 1.7M gates. Moreover, as pointed out in [4], the routing overhead is quite formidable due to the large code length and randomness of the Tanner graph.A joint code and decoder design methodology [5] was recently proposed for (3, k)-regular LDPC code and partly parallel decoder design to achieve appropriate trade-offs between hardware complexity and decoding throughput. In this paper, applying the proposed joint design methodology, we develop an elaborate (3, k)-regular LDPC code highspeed partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder using Xilinx Virtex FPGA device.…”

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A 54 Mbps (3,6)-regular FPGA LDPC decoder

Zhang

Parhi

IEEE Workshop on Signal Processing Systems

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Applying a joint code and decoder design methodology, we develop a high-speed (3, k)-regular LDPC code partly parallel decoder architecture, based on which a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder is implemented on Xilinx FPGA device. When performing maximum 18 iterations for each code block decoding, this partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10 −6 at 2dB over AWGN channel. INTRODUCTIONThanks to its excellent performance, Low-Density ParityCheck (LDPC) code [1][2] has been widely considered as a next-generation error-correcting code for telecommunication and magnetic storage. Defined as the null space of a very sparse M × N parity check matrix H, an LDPC code is typically represented by a bipartite graph, called Tanner graph, in which one set of N variable nodes corresponds to the set of codeword, another set of M check nodes corresponds to the set of parity check constraints and each edge corresponds to a non-zero entry in the parity check matrix H. An LDPC code is known as (j, k)-regular LDPC code if each column and each row in its parity check matrix have j and k non-zero entries, respectively. The construction of LDPC code is typically random. As illustrated in Fig. 1, LDPC code is decoded by the iterative belief-propagation (BP) algorithm [2] that directly matches its Tanner graph. A fully parallel decoder is realized by directly instantiating the BP decoding algorithm to hardware. Such fully parallel decoder could achieve extremely high decoding speed, e.g., a 1024-bit, rate-1/2 LDPC code fully parallel decoder [4] with the maximum symbol throughput of 1 Gbit/s has been implemented using ASIC technology. However, the primary disadvantage of fully parallel design is that with the increase of code length the hardware complexity will become more and more prohibitive for many practical purposes, e.g., the ASIC LDPC decoder [4] with only 1K-bit code length consumes 1.7M gates. Moreover, as pointed out in [4], the routing overhead is quite formidable due to the large code length and randomness of the Tanner graph.A joint code and decoder design methodology [5] was recently proposed for (3, k)-regular LDPC code and partly parallel decoder design to achieve appropriate trade-offs between hardware complexity and decoding throughput. In this paper, applying the proposed joint design methodology, we develop an elaborate (3, k)-regular LDPC code highspeed partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2 (3, 6)-regular LDPC code decoder using Xilinx Virtex FPGA device. We significantly modify the original decoder structure [5] to improve the decoding throughput and simplify the control logic design. We propose a novel concatenated scheme to realize the random connectivity by using two concatenated routing networks, where the random hardwire routings are localized to significantly reduce the routing overhead. Based on the post-routing static timing analysis, with the maximum 18 decoding iterations, this decoder ...

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A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder

Cited by 475 publications

References 15 publications

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

Scheduling Traffic Matrices On General Switch Fabrics

A 54 Mbps (3,6)-regular FPGA LDPC decoder

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