A 68.6fs<sub>rms</sub>-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, A.L.; Levantino, Salvatore

doi:10.1109/isscc42614.2022.9731683

Cited by 10 publications

(1 citation statement)

References 4 publications

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“…Different applications, including SONET, Ethernet, and HDTV, require various levels of jitter, number of output channels, and frequency range [1][2][3]. Research shows that optimization of the loop adaptive tuning mechanism is the paramount factor for multi-protocol compatible clocks [4,5]. For massive MHz telecom services, reasonably designed AFC and MMD are necessary.…”

Section: Introductionmentioning

confidence: 99%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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This paper presents a charge-pump phase-locked loop (PLL) frequency-synthesizer-based low-jitter wideband clock generator for multi-protocol data communications applications. Automatic frequency calibration (AFC) using linear variable time window technology and modified multi-modulus dividers (MMD) based on sub-multi-modulus dividers (SMMD) are developed for faster locking, lower jitter, and implementation of multi-protocol data communications applications. The clock generator is fabricated in 0.18 μm CMOS technology. The measured division ratio of the multi-modulus divider ranges from 1.875 to 25, and the output frequency is 46.875~625 MHz. The lock time does not exceed 30 μs, while jitter is less than 500 fs.

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Section: Introductionmentioning

confidence: 99%

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

et al. 2023

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A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer

Renukaswamy,

Markulic,

Craninckx

2024

PLL Modulation and Mixed-Signal Calibration Techniques for FMCW Radar

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A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter

Feng

Rhee

Wang

2023

2023 IEEE Custom Integrated Circuits Conference (CICC)

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A 68.6fs_rms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

Cited by 10 publications

References 4 publications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer

A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter

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A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching

Cited by 10 publications

References 4 publications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A Low Jitter, Wideband Clock Generator for Multi-Protocol Data Communications Applications

A 16 GHz Duty-Cycled Charge Pump PLL-Based Chirp Synthesizer

A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter

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Product

Resources

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A 68.6fs_rms-total-integrated-jitter and 1.56μs-locking-time fractional-N bang-bang PLL based on type-II gear shifting and adaptive frequency switching