A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

Donnelly, Kevin; Chan, Yiu-Fai; Ho, J.; Tran, Chanh; Patel, Samir N.; Lau, Brian; Kim, Jun; Chau, P.S.; Huang, Ching-Chao; Wei, J.; Yu, Leung; Tarver, R.; Johnson, M.

doi:10.1109/isscc.1996.488623

Cited by 3 publications

(2 citation statements)

References 4 publications

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“…Two common signaling methods are low common-mode (LCM) signaling and high common-mode (HCM) signaling [2], [3], [6]. The two methods result in substantially different transmitter designs and power dissipation.…”

Section: Introductionmentioning

confidence: 99%

A Study of the Optimal Data Rate for Minimum Power of I/Os

Hatamkhani

Yang

2006

IEEE Trans. Circuits Syst. II

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Power dissipation of multi-gigabit per second parallel input-output (I/O) links is an integral part of total integrated circuits (IC) power dissipation. This brief presents an optimal data rate per I/O link at which the power dissipation is minimized. The data rate is expressed as a function of the transmission channel's frequency response. The impact of considering the power due to on-chip electronic switching depends on the process technology of the IC. The analysis results show that an upper bound for the data rate exists based on the channel's frequency response and that the upper bound is being approached with more advanced process technologies.

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Section: Introductionmentioning

confidence: 99%

A Study of the Optimal Data Rate for Minimum Power of I/Os

Hatamkhani

Yang

2006

IEEE Trans. Circuits Syst. II

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“…This digital DLL was integrated into a high-speed memory interface ASIC cell [6] where it served as the clock recovery circuit. It was placed on the same die as a duplicate interface, identical in all respects except that the second interface used a dual-loop, analog DLL [4].…”

Section: Simulated and Measured Performancementioning

confidence: 99%

A portable digital DLL architecture for CMOS interface circuits

Garlepp

Donnelly

Kim

et al.

1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)

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A digital DLL was developed which achieves infinite phase range and 40ps worst-case phase resolution at 400MHz. The architecture uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correctors. This more easily process-portable DLL achieves jitter performance comparable to a more complex analog DLL, when placed into identical highspeed interface circuits fabricated on the same die in a 0.4um CMOS process.

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A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation

Yeung

Horowitz

2000

IEEE J. Solid-State Circuits

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A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

Cited by 3 publications

References 4 publications

A Study of the Optimal Data Rate for Minimum Power of I/Os

A Study of the Optimal Data Rate for Minimum Power of I/Os

A portable digital DLL architecture for CMOS interface circuits

A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation

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