A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation

Yeung, E.; Horowitz, Mark

doi:10.1109/4.881207

Cited by 81 publications

(29 citation statements)

References 19 publications

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“…Cal [1] is set to logic-1, and D 0 [n] = D[n]. In the data transmission mode, Cal [1] is set to logic-0, and the encoding scheme To recover D[n] when n is even, the following scheme is used…”

Section: Encoder and Decodermentioning

confidence: 99%

“…In the calibration mode, training data are sent to D [1],…,D[n], and RefClk. Cal [1] is set to logic-1, and D 0 [n] = D[n].…”

Section: Encoder and Decodermentioning

confidence: 99%

“…2(b), resulting in reduced timing margins. This is known as inter-signal timing skew [1]. Inter-signal timing skew has become a major speed bottleneck of high-speed parallel links.…”

Section: Introductionmentioning

confidence: 99%

“…Point-to-point parallel link interfaces have become popular due to its potential of delivering high I/O bandwidth [1]. Single-ended, fully differential, pseudo differential, voltage-mode incremental, and current-mode incremental signal schemes have been used for point-to-point parallel links [2].…”

Section: Introductionmentioning

confidence: 99%

“…Inter-signal timing skew has become a major speed bottleneck of high-speed parallel links. Perpin skew compensation is typically required to compensate for the misalignment between the reference clock and the data prior to the start of data transmission [1,4]. For parallel links with single-ended or fully differential signaling schemes, clock-like training data are sent to the channels in a calibration phase and digital delay-locked loops are employed at the receiver end to provide a phase adjustment for each channel so that a global sampling clock can be placed at the center of the data eye of all data bits.…”

Section: Introductionmentioning

confidence: 99%

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A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

Yuan

2008

Analog Integr Circ Sig Process

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This paper proposes a new current-mode incremental signaling parallel link interface with per-pin skew compensation. Per-pin skew compensation is carried out in a calibration phase where clock-like training data are sent to all channels along with a reference clock of the same frequency. Training data are deskewed with respect to the common reference clock using DLLs such that all channels are skew-compensated simultaneously. New encoding and decoding scheme have been proposed to reduce the signal critical path at the transmitter. Transimpedance amplifiers with replica biasing are used to perform current-to-voltage conversion at the receiving end with a minimum sensitivity to supply voltage fluctuation. To evaluate the performance of the proposed skew compensating technique, a 1 Gbytes/s parallel link interface consisting of two data channels and one reference clock channel has been implemented with UMC 0.13 lm 1.2 V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BIM3V3 device models. The channels are modeled as 50 X microstrip lines on a FR-4 substrate. Simulation results of the parallel link at all process corners have demonstrated that the proposed parallel link interface provides a minimum deskew range of 1.2 ns (±0.6 ns in each direction).

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Section: Encoder and Decodermentioning

confidence: 99%

“…In the calibration mode, training data are sent to D [1],…,D[n], and RefClk. Cal [1] is set to logic-1, and D 0 [n] = D[n].…”

Section: Encoder and Decodermentioning

confidence: 99%

“…2(b), resulting in reduced timing margins. This is known as inter-signal timing skew [1]. Inter-signal timing skew has become a major speed bottleneck of high-speed parallel links.…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

Yuan

2008

Analog Integr Circ Sig Process

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Wireless Interchip Interconnects

Kikkawa

2012

Advanced Interconnects for ULSI Technology

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IntroductionAccording to the scaling rule of metal-oxide-semiconductor (MOS) transistors in silicon large-scale integrated circuits (LSIs), both operating frequency and power consumption can be improved by reducing the feature sizes of MOS transistors, as shown in Table 15.1 [1]. A system on a chip (SOC) has been developed because it enables the highest packing density of scaled transistors for building an ultra-large-scale integrated circuit system (ULSI). However, the scaling of metal interconnects in an SOC deteriorates the performance of the LSI system because it increases resistance-capacitance (RC) time constants in the metal interconnects, as shown in Table 15.2 [2, 3]. To solve the RC signal delay problems for advanced CMOS technology, new materials such as copper (Cu) and low dielectric constant (low-k) interlayer dielectric films have been introduced [4, 5], as shown in Figure 15.1 (a). Figures 15.1 (b) and (c) are schematic diagrams of complementary MOS (CMOS) inverter circuits connected with a metal interconnect line and its equivalent circuit, respectively [2, 3]. The rise time T 90 % of the output digital signal is expressed aswhere R int , R tr , C int and C L are interconnect resistance, transistor output resistance, interconnect capacitance and load capacitance, respectively. Although the new materials can reduce

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A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

Jarihani

Sturm

Tonello

2021

Circuit Theory & Apps

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This paper presents a high‐speed simultaneous bidirectional transceiver (SBT) for on‐chip wireline communications. A MOS hybrid transistor is utilized to split the received data from the superimposed signal at both ends of the on‐chip interconnection with the assistance of two drivers, namely main and auxiliary. Moreover, a high‐pass filter (HPF) is used as a differentiator to generate the echo cancelation signal. Consequently, the echo‐cancelation for simultaneous bidirectional signaling (SBS) is realized by the combination of the hybrid device and the differentiator. The proposed SBT has been designed and evaluated using 28‐nm CMOS technology over a narrow 5‐mm on‐chip interconnection, which possesses 11.9‐dB loss at the Nyquist frequency (half a bit rate). The energy‐efficiency of the proposed full‐duplex transceiver (FDT) for 20‐Gbps simultaneous bidirectional data transmission is 0.147 PJ/b/mm. The performance results show that the proposed SBT has better overall performance compared to the previous architectures reported in the literature to date. The layout of the presented SBT occupies a low area of 1574 μm2.

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A 2.4 Gb/s/pin simultaneous bidirectional parallel link with per-pin skew compensation

Cited by 81 publications

References 19 publications

A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

A new parallel link interface with current-mode incremental signaling and per-pin skew compensation

Wireless Interchip Interconnects

A full‐duplex transceiver for 20‐Gbps high‐speed simultaneous bidirectional signaling across global on‐chip interconnections

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