A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliability

Yasuda, Y.; Kimizuka, N.; Iwamoto, Toshiyuki; Fujieda, Shinji; Ogura, Takashi; Watanabe, H.; Tatsumi, T.; Yamamoto, Ichiro; Ito, K.; Yamagata, Y.; Imai, K.

doi:10.1109/vlsit.2004.1345381

Cited by 11 publications

(9 citation statements)

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“…Figure 11 shows TDDB failure distribution for HK/MG pMOSFETs on various stress bias conditions. Unlike nMOSFET, the IL degradation by hole traps is primary cause to breakdown of pMOSFET at gate injection bias [1]. Such that after BD severe G m degradation was observed without SILC generation.…”

Section: Methodsmentioning

confidence: 99%

“…To date Hf-based high-k dielectric/metal gate stack (HK/MG) CMOSFETs have enabled very aggressive equivalent -oxide-thickness (EOT) scaling due mainly to less gate leakage achieved by relatively thicker physical thickness than conventional silicon oxynitride (SiON) dielectrics for the same EOT [1][2]. However, such aggressive gate stack scaling often suffers from time dependent dielectric breakdown (TDDB) and, in effect, an accurate lifetime estimation becomes a crucial reliability concern in terms of test methodology and modeling.…”

Section: Introductionmentioning

confidence: 99%

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Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

Lee

Nam

Jin

et al. 2011

2011 International Reliability Physics Symposium

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The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (t bd ) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, t bd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter t bd than with DC at a lower frequency. This is attributed to hole trapping into IL as V g is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer t bd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because G m degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.

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Section: Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

Lee

Nam

Jin

et al. 2011

2011 International Reliability Physics Symposium

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“…In order to reduce the standby power consumption for LSTP applications, both the gate leakage and the off-state drain current, which includes gate-induced drain leakage (GIDL), must be reduced effectively. 1) In addition, gate leakage becomes a serious problem even for high-performance application because of the huge gate leakage observed with thin SiON gate dielectrics. Developing an integration scheme to reduce gate leakage without performance degradation is definitely one of the biggest concerns for future technology.…”

Section: Introductionmentioning

confidence: 99%

“…However, up till now, not many studies have addressed this point. 1,6) To achieve high performance and reliability, transistor design schemes, particularly processes surrounding gate dielectrics, are essential, such as gate-electrode and offset-spacer as well as thermal budget controls after the gate formation. Also, an appropriate methodology for time-dependent dielectric breakdown (TDDB) evaluation must be introduced for degradation mechanism identification.…”

Section: Introductionmentioning

confidence: 99%

Low Stand-by Power HfSiON Transistor Design Scheme Ensuring Both Performance and Time Dependent Dielectric Breakdown Lifetime for 65 nm Node and Beyond

Yasuda¹,

Yamamoto²,

Takano³

et al. 2007

jjap

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We have proposed a 65 nm node low stand-by power (LSTP) HfSiON/base-SiO 2 transistor design scheme ensuring both high performance and reliability at the same time. In particular, a process condition around the gate was carefully designed. It was found that a low temperature SiO 2 offset-spacer could remove the nonintrinsic factor for time-dependent dielectric breakdown (TDDB) without performance degradation. Moreover, a method of monitoring gate leakage after gate dielectric breakdown has been introduced to improve TDDB lifetime. This method can sense extrinsic factors that induce TDDB lifetime degradation. Using this method, we successfully eliminated extrinsic factors that are related to process conditions. Consequently, TDDB lifetime can be guaranteed at V dd ¼ 1:2 V without performance degradation.

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“…To enhance body-bias effect even for the reduced gate-length of 45-nm, super steep retrograde channel and halo have been optimized [4]. Moreover, for low standby power CMOS devices, in which gate leakage and GIDL are the dominant components of leakage current, we have adopted high-k gate dielectric film [5]. By exploiting "Fermi-pinning effect" of polysilicon gate/HfSiON film interface, we have effectively suppressed GIDL current as well as gate leakage current.…”

Section: Introductionmentioning

confidence: 99%

Device Technology for Body Biasing Scheme

Imai

Yamagata

Masuoka

et al.

2005 IEEE International Symposium on Circuits and Systems

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Abstract-We report power-aware 65-nm node CMOS device technology suitable for body biasing scheme. For highperformance CMOS, both channel and halo profiles have been optimized to enhance the body-bias effect of 45-nm gate length devices. Standby leakage reduction without device reliability compromise has been demonstrated with simultaneous voltage control of body bias and power supply. Moreover, high-k gate dielectric "HfSiON" has been adopted to reduce both gate leakage and GIDL, which are the dominant standby leakage components of low standby power CMOS.

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A 65nm-node LSTP (Low standby power) poly-Si/a-Si/HfSiON transistor with high I/sub on/-I/sub standby/ ratio and reliability

Cited by 11 publications

References 0 publications

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

Low Stand-by Power HfSiON Transistor Design Scheme Ensuring Both Performance and Time Dependent Dielectric Breakdown Lifetime for 65 nm Node and Beyond

Device Technology for Body Biasing Scheme

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