Low Stand-by Power HfSiON Transistor Design Scheme Ensuring Both Performance and Time Dependent Dielectric Breakdown Lifetime for 65 nm Node and Beyond

Abstract

We have proposed a 65 nm node low stand-by power (LSTP) HfSiON/base-SiO 2 transistor design scheme ensuring both high performance and reliability at the same time. In particular, a process condition around the gate was carefully designed. It was found that a low temperature SiO 2 offset-spacer could remove the nonintrinsic factor for time-dependent dielectric breakdown (TDDB) without performance degradation. Moreover, a method of monitoring gate leakage after gate dielectric breakdown has been introduced to improve TDDB lifetime. This method can sense extrinsic factors that induce TDDB lifetime degradation. Using this method, we successfully eliminated extrinsic factors that are related to process conditions. Consequently, TDDB lifetime can be guaranteed at V dd ¼ 1:2 V without performance degradation.