Device Technology for Body Biasing Scheme

Imai, K.; Yamagata, Y.; Masuoka, S.; Kimuzuka, N.; Yasuda, Y.; Togo, M.; Ikeda, Masayuki; Nakashiba, Y.

doi:10.1109/iscas.2005.1464512

Cited by 10 publications

(6 citation statements)

References 6 publications

(7 reference statements)

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“…Previous works [17], [18] have shown that for thinner gate oxides, the amount of degradation due to NBTI increases with an increase in Î . This is caused by increased electric fields that result in higher rates of breakdown of the weak Ë À bonds according to the equations [4], [13]:…”

Section: E ¡î ø Dependence On Supply Voltagementioning

confidence: 90%

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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Abstract-Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of Hf-based high-k dielectrics for gate leakage reduction, Positive Bias Temperature Instability (PBTI), the dual effect in NMOS transistors has also reached significant levels. Consequently, designers are required to build in substantial guardbands into their designs, leading to large area and power overheads, in order to guarantee reliable operation over the lifetime of a chip. We propose a guard-banding technique based on adaptive body bias (ABB) and adaptive supply voltage (ASV), to recover the performance of an aged circuit, and compare its merits over previous approaches.

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Section: E ¡î ø Dependence On Supply Voltagementioning

confidence: 90%

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Kumar

Sapatnekar

2009

2009 Asia and South Pacific Design Automation Conference

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“…Therefore, there exists an optimum RBB value that yields the lowest combined subthreshold and BTBT leakage, and this RBB value decreases in magnitude as the technology scales [23]. However, some works such as [25] have successfully implemented a RRB technique in a 65nm technology node by optimizing the device parameters.…”

Section: Discussionmentioning

confidence: 99%

Impact of technology scaling on leakage reduction techniques

Ghafari

Anis

Elmasry

2007

2007 IEEE Northeast Workshop on Circuits and Systems

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CMOS technology is scaling down to meet the performance, production cost, and power requirements of the microelectronics industry. The increase in the transistor leakage current is one of the most important negative side effects of technology scaling. Leakage affects not only the standby and active power consumption, but also the circuit reliability, since it is strongly correlated to the process variations. Leakage current influences circuit performance differently depending on: operating conditions (e.g., standby, active, burn in test), circuit family (e.g., logic or memory), and environmental conditions (e.g., temperature, supply voltage). Until the introduction of high-K gate dielectrics in the lower nanometer technology nodes, gate leakage will remain the dominant leakage component after subthreshold leakage.[1] Since the way designers control subthreshold and gate leakage can change from one technology to another, it is crucial for them to be aware of the impact of the total leakage on the operation of circuits and the techniques that mitigate it.Consequently, techniques that reduce total leakage in circuits operating in the active mode at different temperature conditions are examined. Also, the implications of technology scaling on the choice of techniques to mitigate total leakage are investigated. This work resulted in guidelines for the design of low-leakage circuits in nanometer technologies. Logic gates in the 65nm, 45nm, and 32nm nodes are simulated and analyzed. The techniques that are adopted for comparison in this work affect both gate and subthreshold leakage, namely, stack forcing, pin reordering, reverse body biasing, and high threshold voltage transistors. Aside from leakage, our analysis also highlights the impact of these techniques on the circuit's performance and noise margins.The reverse body biasing scheme tends to be less effective as the technology scales since this scheme increases the band to band tunneling current. Employing high threshold voltage transistors seems to be one of the most effective techniques for reducing leakage with minor performance degradation. Pin reordering and natural stacks are techniques that do not affect the performance of the device, yet they reduce leakage. However, it is demonstrated that they are not as effective in all types of logic since the input values might switch only between the highly leaky states.Therefore, depending on the design requirements of the circuit, a combination, or hybrid iii of techniques which can result in better performance and leakage savings, is chosen. Power sensitive technology mapping tools can use the guidelines found as a result of the research in the low power design flow to meet the required maximum leakage current in a circuit. These guidelines are presented in general terms so that they can be adopted for any application and process technology. iv AcknowledgementsThis research project would not have been possible without the support of many people.

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“…2) Therefore, much work for reducing the initial I OFF has been researched. [3][4][5][6][7][8][9][10] Among them, the variable body bias technique is an attractive method because it decreases the initial I OFF only at a reverse body bias without any change in the process. 7) The various stresses during the device operation can also increase the initial I OFF .…”

Section: Introductionmentioning

confidence: 99%

Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

Kang

Kim

Lee

et al. 2016

Jpn. J. Appl. Phys.

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The effect of the reverse body bias V SB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse V SB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field E m due to the increase in the threshold voltage V th. The sensitivity of HEIP degradation to V SB increased with increasing body effect coefficient γ at a given oxide thickness T ox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on V SB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

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Device Technology for Body Biasing Scheme

Cited by 10 publications

References 6 publications

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Adaptive techniques for overcoming performance degradation due to aging in digital circuits

Impact of technology scaling on leakage reduction techniques

Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

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