A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC

Jeong, Minsu; Kim, Bonkee; Cho, Young-Ho; Kim, Yang‐Gyun; Kim, Se-Yeob; Yoo, Heeyong; Lee, Jung Hwan; Lee, Jae Kwan; Jung, Kyung Soo; Lee, Jeiyoung; Lee, Jung-Hun; Yang, Haoran; Taylor, Gerry; Kim, Bo-Eun

doi:10.1109/isscc.2010.5433850

Cited by 18 publications

(8 citation statements)

References 4 publications

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“…In Table I, the measured results are summarized with those of state-of-the-art low power mobile TV receivers [4], [12]. The NF and IIP3 performances of the proposed receiver are comparable to those of [4] in FM and T-DMB bands and better NF in DAB L-band.…”

Section: Measurement Resultsmentioning

confidence: 93%

“…Among various reported mixers, the current commutating passive mixer is one of the most preferred solutions for those performances [1][2][3][4].…”

Section: B Mixer and Switched-capacior Filtermentioning

confidence: 99%

“…To improve the linearity of mixer, a well-known method is adopting an opamp-based transimpedance amplifier (TIA) with low input impedance at the output of switching quad [1][2][3][4]. However, the small output impedance of the TIA shows that the mixer output behavior is voltage mode not current mode, which is required to drive a built-in anti-aliasing charge-domain SCF.…”

Section: B Mixer and Switched-capacior Filtermentioning

confidence: 99%

“…To support various applications, the multi-standard multi-band RF tuners are developed considering power, cost and size efficiencies with zero-/low-IF architectures [1,2]. Mobile TV system-on-chip (SoC) approach further increases the level of integration and functionality by integrating the RF tuner, ADC, baseband demodulator into a single chip [3,4]. The multi-standard multi-band TV SoC design reported in [4] achieves a significant reduction in chip area and power consumption by doing baseband processing tasks which include channel selection, image rejection filtering and DC offset cancellation in digital domain.…”

Section: Introductionmentioning

confidence: 99%

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A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip

Nguyen

Jung

Min

et al. 2011

2011 Proceedings of the ESSCIRC (ESSCIRC)

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This paper presents a low power discrete-time receiver supporting three broadcast services FM, T-DMB and DAB. To meet the requirement of sensitivity, three LNAs are implemented to cover each band. The proposed mixer core is terminated by a common-gate current buffer to improve linearity and merged with a switched-capacitor sampled filter in current mode for low power and low complexity. The filter performs the second-order low-pass filtering with anti-aliasing ratio up to 70 dB at 1.6 MHz bandwidth. The chip is fabricated in a 90 nm CMOS technology and dissipates 11 mA current from 1.2 V supply. The receiver shows 48 dB maximum gain, 60 dB gain control range, 2.7 dB noise figure, and -22/0 dBm IIP3 in LNA high/low gain mode.

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Section: Measurement Resultsmentioning

confidence: 93%

“…Among various reported mixers, the current commutating passive mixer is one of the most preferred solutions for those performances [1][2][3][4].…”

Section: B Mixer and Switched-capacior Filtermentioning

confidence: 99%

Section: B Mixer and Switched-capacior Filtermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip

Nguyen

Jung

Min

et al. 2011

2011 Proceedings of the ESSCIRC (ESSCIRC)

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“…Cost pressures have resulted in substantial integration of analog and digital blocks on the same die, forcing analog designers to adapt to processes that were built for digital systems [1,2]. As we rapidly approach the physical limits of scaling, one of the major challenges for analog circuits has been to ensure consistently high yield in the presence of increasing variability in these nanoscale CMOS processes.…”

Section: Introductionmentioning

confidence: 99%

Statistical modeling and post manufacturing configuration for scaled analog CMOS

Keskin

Proesel

Pileggi

2010

IEEE Custom Integrated Circuits Conference 2010

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Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g., offset). Silicon results from a 65nm test chip demonstrate that SES can achieve an order of magnitude better matching than both redundancy and Pelgrom-model sizing given the same core circuit area. I. INTRODUCTIONContinuous advancement of CMOS process technology over the past four decades has made inexpensive integrated circuit products with significant processing capabilities an everyday reality. Cost pressures have resulted in substantial integration of analog and digital blocks on the same die, forcing analog designers to adapt to processes that were built for digital systems [1,2]. As we rapidly approach the physical limits of scaling, one of the major challenges for analog circuits has been to ensure consistently high yield in the presence of increasing variability in these nanoscale CMOS processes.In this paper we explore the benefits of a statistical element selection (SES) methodology for analog circuits that is based on post-manufacturing tuning to accommodate large-scale process variations [3,4]. SES exploits inherent random variations to improve the matching of transistors and to increase yield for matching-critical circuits such as comparators. A subset of k elements is selected among an identically laid out set of N elements to provide the best matching performance. As the number of available subsets among a set of N elements increases exponentially (2 N -1), it is possible to achieve impressive matching performance with near-minimum size unit elements. The elements might be individual transistors, pairs of transistors, or passive components.We present a general methodology to determine the appropriate (N, k) numbers and the size of the unit element to ensure that a desired matching specification is met. We present measurement results from a 65nm CMOS test chip using SESbased comparators to validate the model predictions. The generalized methodology can be used for a wide variety of analog circuits-such as current sources, differential amplifiers and comparators-that rely on precise matching of components.

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A Mixed-Voltage Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS

Mak

Martins

2012

Analog Circuits and Signal Processing

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A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC

Cited by 18 publications

References 4 publications

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip

Statistical modeling and post manufacturing configuration for scaled analog CMOS

A Mixed-Voltage Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS

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