Statistical modeling and post manufacturing configuration for scaled analog CMOS

Abstract

Process variations in advanced CMOS process nodes limit the benefits of scaling for analog designs. In the presence of increasing random intra-die variations, mismatch becomes a significant design challenge in circuits such as comparators. In this paper we describe and demonstrate the details of a statistical element selection (SES) methodology that relies on choosing a subset of selectable circuit elements (e.g., input transistors in a comparator) to achieve the desired specification (e.g., offset). Silicon results from a 65nm test chip demonstrate that SES can achieve an order of magnitude better matching than both redundancy and Pelgrom-model sizing given the same core circuit area. I. INTRODUCTIONContinuous advancement of CMOS process technology over the past four decades has made inexpensive integrated circuit products with significant processing capabilities an everyday reality. Cost pressures have resulted in substantial integration of analog and digital blocks on the same die, forcing analog designers to adapt to processes that were built for digital systems [1,2]. As we rapidly approach the physical limits of scaling, one of the major challenges for analog circuits has been to ensure consistently high yield in the presence of increasing variability in these nanoscale CMOS processes.In this paper we explore the benefits of a statistical element selection (SES) methodology for analog circuits that is based on post-manufacturing tuning to accommodate large-scale process variations [3,4]. SES exploits inherent random variations to improve the matching of transistors and to increase yield for matching-critical circuits such as comparators. A subset of k elements is selected among an identically laid out set of N elements to provide the best matching performance. As the number of available subsets among a set of N elements increases exponentially (2 N -1), it is possible to achieve impressive matching performance with near-minimum size unit elements. The elements might be individual transistors, pairs of transistors, or passive components.We present a general methodology to determine the appropriate (N, k) numbers and the size of the unit element to ensure that a desired matching specification is met. We present measurement results from a 65nm CMOS test chip using SESbased comparators to validate the model predictions. The generalized methodology can be used for a wide variety of analog circuits-such as current sources, differential amplifiers and comparators-that rely on precise matching of components.

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

“…Since the number of available combinations increases exponentially as N and K increase, the approach provides for an exponential number of design choices that can be digitally selected. This design method has been successfully applied to comparator design in [12] and current-steering D/A data converter design in [13]. With the capability of countering random mismatch with minimum analog circuits overhead involved, the SES method has been considered as a suitable analog circuit design methodology in sub-20 nm CMOS technology nodes [14].…”

“…Gain mismatch and phase mismatch were decoupled and calibrated independently following an extended version of statistical element selection (SES) [12]. Phase mismatch for HRR 2,4,6 was also calibrated.…”

“…The SES design and calibration methodology for analog circuits [12] is based on creating combinatorial redundancy by digitally selecting K elements from a set of N equal elements, leaving N-K elements sacrificed. Since the number of available combinations increases exponentially as N and K increase, the approach provides for an exponential number of design choices that can be digitally selected.…”

Indirect phase noise sensing for self-healing voltage controlled oscillators

“…Traditional overdesign technique, whereby the circuit is designed to perform better than the specifications with large margins for variability, is becoming impractical for high performance circuits. Process variability and the push to higher performance cause unpredictable and unacceptable product yield that requires self-healing design methodologies based on post-manufacturing tuning [1,2]. Self-healing design enables the circuit to calibrate itself not only for varying process but also for varying environment and circuit conditions that can degrade the performance.…”

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion

“…As the traditional over-design technique becomes impractical, on-chip self-healing has emerged as a promising methodology to address the variability issue [4]- [5]. The key idea of self-healing is to actively monitor the post-manufacturing circuit performance metrics and then adaptively adjust a number of tuning knobs (e.g., bias current) in order to meet the given performance specifications.…”