A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Pilo, H.; Arsovski, Igor; Batson, Kevin; Braceras, G.; Gabric, J.; Houle, R.; Lamphier, S.; Pavlik, Frank; Seferagic, Adnan; Chen, Liang‐Yu; Ko, Shang-Bin; Radens, C.

doi:10.1109/jssc.2011.2164730

Cited by 51 publications

(16 citation statements)

References 3 publications

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“…Pilo et al [14] uses a regulator to precharge bitlines to around 70% of Vdd to improve yield from 5 to 5.7 sigma or, equivalently, from a BER of 2.9 · 10 −7 to 6 · 10 −9 . IS analysis of read stability confirmed their results, with a BER improvement of around 1.5 orders of magnitude at 0.7 V. However, the assist becomes less helpful at low supplies and only achieves a Vmin reduction of 25 mV.…”

Section: ) Effect Of Cell Vdd Collapse As a Writeability Assistmentioning

confidence: 99%

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer

Toh

et al. 2012

IEEE Trans. Circuits Syst. II

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Section: ) Effect Of Cell Vdd Collapse As a Writeability Assistmentioning

confidence: 99%

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

Zimmer

Toh

et al. 2012

IEEE Trans. Circuits Syst. II

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“…Otherwise, the wordline voltage is applied consecutively low-to-high to limit noise-injection at a short time. Then, bitlines are suppressed with the additional supply voltage [7]. Meanwhile, the write margin (WRM) is increased by driving negative voltage to bitline [6], [7] or by lowering the of bitcell [4], [8].…”

Section: Introductionmentioning

confidence: 99%

“…Then, bitlines are suppressed with the additional supply voltage [7]. Meanwhile, the write margin (WRM) is increased by driving negative voltage to bitline [6], [7] or by lowering the of bitcell [4], [8]. The conventional assist-schemes can improve the ADM and the WRM of SRAM with a trade-off of performance, power, and area.…”

Section: Introductionmentioning

confidence: 99%

A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Song

Rim

Jung

et al. 2015

IEEE J. Solid-State Circuits

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Two 128 Mb dual-power-supply SRAM chips are fabricated in a 14 nm FinFET technology. A 0.064 m and a 0.080 m 6T SRAM bitcells are designed for high-density (HD) and high-performance (HP) applications. To improve of the high-density SRAM, a negative bitline scheme (NBL) is adopted as a write-assist technique. Then, the disturbance-noise reduction (DNR) scheme is proposed as a read-assist circuit to improve the of the high-performance SRAM. The 128 Mb 6T-HD SRAM test-chip is fully demonstrated featuring 0.50 with 200 mV improvement by NBL, and 0.47 for the 128 Mb 6T-HP with 40 mV improvement by the DNR. Improved reduces 45.4% and 12.2% power-consumption of the SRAM macro with the help of each assist circuit, respectively.

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“…The large-scale SRAM margin metrics can be directly measured through the bit lines (i.e., without using the padded-out SRAM cells). Therefore, the large-scale SRAM margin metrics are adequate for the state-of-art large-scale SRAM arrays (e.g., 64 Mb SRAM arrays [23], which include 64 × 2 20 cells on a single chip). In this chapter, we will study the conventional SRAM margin metrics and the large-scale SRAM margin metrics; the conventional SRAM margin metrics are still the most widely used SRAM margin metrics, and are well associated with the large-scale SRAM margin metrics.…”

Section: Metrics For Sram Read/write Noise Marginmentioning

confidence: 99%

Applications in Static Random Access Memory (SRAM)

Shin

2016

Variation-Aware Advanced CMOS Devices and SRAM

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Continuous efforts to shrink the physical size of transistors enable the integration of a larger number of transistors on a single chip. Today, it is feasible to fabricate a single SRAM cell in a 0.04999-µm 2 area [1]. However, as the transistors are aggressively scaled down, the impacts of the process-induced random variations on the device performance are dramatically increased [2]. The term "process-induced random variations" indicates that the process/fabrication steps such as doping, lithography, etching, chemical mechanical polishing (CMP), and so on, induce these random variations [3]. The well-known random variation sources caused by the aforementioned process steps are random dopant fluctuations (RDF) [4] [also known as random dopant distributions (RDD)] [5], line edge roughness (LER) [6], work function variations (WFV) [7] (also known as metal grain granularity (MGG) [8]), and oxide thickness variations [9]. Aforementioned random variations cause variations in parameters such as effective channel length and threshold voltage of each transistor. Then, the mismatches in the effective channel lengths and threshold voltages between two neighboring transistors cause degradations in the stability of the SRAM cells, which consist of a few transistors (e.g., 6 transistors for 6T SRAM cell) [10]. This is because each transistor of a single SRAM cell should be balanced in order to make it stable for the read/write/retention operations [11]. Further detailed information about how to balance the different transistors of a single SRAM cell, and how badly the stabilities of the SRAM cells are degraded by process-induced variations, will be provided later.Since random variations significantly affect the performance of SRAM cells, it is irrefutable that random variations are one of the key factors in the SRAM cell design. Furthermore, it is important to look for "random variation"-tolerant SRAM designs because random variations cannot be controlled, as systematic variations are controlled [12]. In order to find the random-variation-tolerant SRAM cell designs, understanding how the SRAM cell operates and how the process-induced

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A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements

Cited by 51 publications

References 3 publications

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS

A 14 nm FinFET 128 Mb SRAM With V<formula formulatype="inline"> <tex Notation="TeX">$_{\rm MIN}$</tex></formula> Enhancement Techniques for Low-Power Applications

Applications in Static Random Access Memory (SRAM)

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