A 6-bit 38 GHz SiGe BiCMOS phase shifter for 5G phased array communications

A 6-bit digitally controlled active phase shifter is implemented in 0.13-µm SiGe BiCMOS process for 6-18 GHz phased-arrays. An input passive balun with center open stub is applied to split the single input to differential and achieve high amplitude/phase balance. A degenerated-Q quadrature all-pass filter (QAF) is used to generate two orthogonal vectors with high I/Q accuracy over a wide bandwidth and a main digital-toanalog convertor (DAC) controls the I/Q amplitude to achieve 6-bit phase resolution. In addition, a calibration DAC is adopted to compensate the amplitude variations and the phase error introduced by balun and QAF. Consequently, high resolution along with low gain/phase error can be achieved. The phase shifter has achieved root mean square (RMS) phase error of <4.36°, and RMS gain error of <1.04 dB for all 6-bit phase states at 6-18 GHz. The power gain ranges from 0.95 dB at 6 GHz to −1.85 dB at 18 GHz. Input 1 dB compression point (IP −1dB) is 5.4-8 dBm at 6-18 GHz for 0°-phase state. The total power consumption is 74.4 mW, and the overall chip size is 1.8 × 1.3 mm 2 .

Section: Quadrature All-pass Filter (Qaf)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 6–18 GHz 6-bit active phase shifter in 0.13-µm SiGe BiCMOS

Luo

Yao

et al. 2019

“…Phase shifters are essential components in phased-array transceivers. Among various circuit topologies, the vector-summing architecture [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18] is extensively used for the design of active phase shifters. The block diagram and operating principle of a generic vectorsumming phase shifter are shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

Magnetically coupled quadrature all-pass filter for quadrature signal generation in vector-summing phase shifters

Hsu

2021

For a vector-summing phase shifter, the quadrature signal generation (QSG) network is crucial. Among the existing QSG networks, a one-stage quadrature all-pass filter (QAF) provides the same bandwidth as a two-stage -polyphase filter while exhibiting 6-dB higher voltage gain. Despite all the advantages, the major disadvantage of the conventional QAF is that it contains two inductors, which occupy large chip area. In this work, magnetically coupled QAF (MCQAF) is proposed. In the proposed MCQAF, the two inductors in the QAF are intertwined to reduce the occupied chip area, dispelling the major disadvantage of the conventional QAF. With the magnetic coupling between the inductors considered, the design equation for the inductance in the MCQAF is derived. An MCQAF is designed at 2 GHz in a GaAs integrated passive device process along with a conventional QAF for comparison. The results of this work show that, except for a slightly larger amplitude error, the proposed MCQAF exhibits performances comparable to those of the conventional QAF while the occupied chip area is reduced by approximately 1/3.

“…True-time delay lines (TTDL) and phase shifters are widely used in RF and microwave applications, especially in phased-array antennas and radars [1,2,3,4,5,6,7,8]. A simple transmission line could work as a fixed time delay line.…”

Section: Introductionmentioning

confidence: 99%

A novel tunable true-time delay line/phase shifter based on distributed Schottky structure

Pen

Huang

Wang

et al. 2019

True time delay lines and phase shifters are widely used in RF timed/phased array systems. Conventional delay lines and phase shifters often associate with reflection type circuits or distributed (periodically loaded) transmission lines. In this paper, we propose a new type of distributed circuit which composed of uniform transmission lines built on integrated Schottky active layer. A bi-functional chip is designed based on the new distributed structure. An Archimedean spiral topology is adopted to reduce the chip area. Theoretical analysis of the design method and circuit parameters is performed and a miniaturized prototype is implemented with p-HEMT technology to validate the design theory. Measurement results shows that this chip could work as either an areaefficient true-time delay line or a low-voltage phase shifter over the bandwidth 11-15 GHz. As an area-efficient true-time delay line, this chip provides 82.1 ps delay time per square millimeter when the biasing voltage fixed at −1.4 V. As a low-voltage phase shifter, this chip provides 26.43°p hase shift per volt when the biasing voltage sweeps form 0 V to −1.4 V.