A 6-10 bits Reconfigurable 20MS/s Digitally Enhanced Pipelined ADC for Multi-Standard Wireless Terminals

Abstract

A 20MS/s pipelined ADC architecture can be reconfigured in 10 clock cycles to resolve 6, 8, 9 or 10 bits at maximum resolution. A 9.1bit ENOB and 74dB SFDR with a power consumption of only 8mW was achieved by using background digital calibration and op-amp sharing techniques. The test chip, containing two ADC for I and Q processing within a wireless receiver, has been realized in a 0.13µ µ µ µm pure CMOS technology and uses 3.2mm 2 silicon area.

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Implementation Challenges

“…This sets a need to have resolution tuning as an important feature of the ADCs. Variable resolution ADCs allow reducing the power consumption when a medium or low resolution mode is used [43], [49]- [53]. For example, the resolution-tunable ADC reported in [43] consumes 1.6 mW at 18 bit resolution, while it consumes only 0.39 mW when running at 11 bit resolution.…”

“…A pipelined ADC given in [52] allows tuning resolution from 10 to 12 bits, which does not meet some sensor interface requirements. A wider resolution tuning range (from 6 to 10 bits) is offered by the pipelined ADC in [53]. Also, a 5 to 10 bit design was presented in [49].…”