A 54*54-b regularly structured tree multiplier

Transition reduction in carry-save adder trees

“…The even cell contains 68 transistors when XOR gates are assumed implemented with 10 transistors. The complexity and speed of this 4-2 is similar to the common 4-2 cell used in [4], which has 58 transistors when buffering both Cry and Sum. Both circuits have a critical path equal to 3 XOR gates from the a,b,c,d inputs to the sum output.…”

“…The best results were obtained by using the even/ [4] combination where the odd 4-2 compressor is replaced with that described in [4]. The compressor in [4] has a similar truth table to the odd compressor but can be implemented with a simpler (and therefore more power efficient) circuit.…”

“…The effect of this feedback is that the 4-2 compressor behaves as an even 4-2 when the output of the carry flip-flop is 1 and as an odd 4-2 when the output is 0. Assuming random inputs with 50% transition probability at a, b, c, d and C in , Table II shows the probability of having a valid transition (ignoring glitches) at the C out , Cry and Sum outputs of several 4-2 compressors: using 2 full adders, the circuit given in [4], and the proposed even, odd and feedback circuit. The probability of having Cry=0 is shown on the right, which indicates that a skewed probability gives reduced number of transitions.…”

“…High-speed multipliers [4,5] often contain a Wallace tree of carry-save adders to sum the partial products. The most commonly used circuit is the 4-2 compressor (5-3 counter) shown in Fig.…”

High-performance left-to-right array multiplier design

“…To improve regularity and compact layout, regularly structured tree (RST) with recurring blocks [6] and rectangular-styled tree by folding [8] were proposed, at the expense of more complicated interconnects. In [15], three dimensional minimization (TDM) algorithm was developed to design adders of the maximal possible size with optimized signal connections, which further shortened the PPR path by 1 ∼ 2 XOR delays.…”