Transition reduction in carry-save adder trees

A new 4-2 adder and booth selector for low power MAC unit

“…The simulation results show that the newly designed 4-2 adder in the Wallace tree dissipates lower power than the previously reported result [2] by 16% without increasing time delay. By designing a new 4-2 adder and a Booth selector we reduced the power dissipation, and we reduced total number of MOS transistors by 28% as shown in Figure 8.…”

“…Thus, Table 2 shows that the proposed 4-2 adder circuits have lower number of transistors and reduce the power consumption by 16% compared to the previous 4-2 adder [2]. Figure 5(b) shows the proposed 4-2 [nsec]…”

A low-power digital matched filter for direct-sequence spread-spectrum signal acquisition

“…A common disadvantage in this approach is that a lot of spurious transitions will occur due to disparate propagation delays in different signal paths. To solve this problem, one may adopt compressors with higher compression ratios, and match the path delay among compressors [19], [20]. In this scheme, the inputs of each compressor are changed simultaneously, which implies the propagation delay of interconnections between compressors needs be controlled carefully.…”

“…Compressor design is the crucial element in the success of the high-rate compression scheme. Most literature focuses on the 4-2 compressor design, which is shown to be more power-saving than cascaded full-adder-based compressors [19], [20]. The design of higher rate compressors is more challenging because the logic complexity grows exponentially with the number of input bits.…”

“…The power consumption of the pad ring is excluded in this measurement. The functionality of the test chip is verified using a logic analyzer and a pattern generator that provides input patterns with different clock periods (10,20,25,40,50, 100 ns, ). At 5-V supply voltage, the test chip can operate up to 50 MHz.…”