A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

Chawla, R.; Bandyopadhyay, Abhishek; Srinivasan, Venkatesh; Hasler, P.

doi:10.1109/cicc.2004.1358910

Cited by 31 publications

(29 citation statements)

References 10 publications

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“…3, every FGPFET in the array, coupled with the respective row's log amp, forms a wide range, programmable gain current mirror. The current mirror utilizes the sources of the transistors for signal propagation instead of the gates, as in [9], minimizing power law errors due to mismatches in gate-to-surface coupling. Each quadruplet of VMM FGPFETs corresponds to one coefficient in B.…”

Section: Current Based Vector Matrix Multiplication Designmentioning

confidence: 99%

A 256×256 separable transform CMOS imager

Robucci

Gray

Abramson

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper discusses a 256x256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and inpixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8x8 general separable 2-D convolutions as well as 16x16 block transforms.Modern CMOS imagers are opening a new field of possibilities for combining image sensing and processing. CCD based image sensors previously dominated the camera market, producing high-quality results, but they have the limitation of needing special processes that do not allow for high levels of on-chip integration. Also, CCDs require high voltage generation and consume higher power than CMOS imagers. CMOS imaging technology, on the other hand, can be implemented on standard, relatively low-cost CMOS processes. By integrating circuit components into the image sensor, such as in-pixel ADC's [1], CMOS technology has become competitive in the high-end camera market. Other aggressive circuit integrations in CMOS imaging technology provide additional computationally significant gains, such as random image access [2], dynamic field of view capabilities [3], multi-resolution image sensing [4], and biologically inspired abilities such as edge enhancement [5].Our computational image sensor approach aims to implement many of the aforementioned features in a reconfigurable platform. By integrating focal-plane computation with peripheral analog computation circuitry, a variety of linear transformations can be performed. Integrating non-volatile analog memory and a versatile random access approach allows a variety of behaviors like multi-resolution and selective sensing. This work advances the circuit designs and concepts in previous work [6], which implemented a block transform imager system. In particular, advancements were made amongst the low-level circuit topologies, including current sensing circuits, pixel structure, and the analog memory, along with the choice of the vector matrix multiplier design. The components were designed to target support for larger imagers.

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Section: Current Based Vector Matrix Multiplication Designmentioning

confidence: 99%

A 256×256 separable transform CMOS imager

Robucci

Gray

Abramson

et al. 2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…1). Though large-signal current-mode MAC structures [8] are available, a small-signal implementation with a fixed current can achieve a better power-bandwidth trade-off. In this work, we present a compact resistor-less differential MS-N with PMOS load which operate in small-signal mode, and is energy-efficient over a large range of bias currents.…”

Section: Introductionmentioning

confidence: 99%

An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems

Chatterjee¹,

Panda²,

Maity³

et al. 2017

2017 IEEE International Conference on Rebooting Computing (ICRC)

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This work presents the design and analysis of a mixed-signal neuron (MS-N) for convolutional neural networks (CNN) and compares its performance with a digital neuron (Dig-N) in terms of operating frequency, power and noise. The circuitlevel implementation of the MS-N in 65 nm CMOS technology exhibits 2-3 orders of magnitude better energy-efficiency over Dig-N for neuromorphic computing applications -especially at low frequencies due to the high leakage currents from many transistors in Dig-N. The inherent error-resiliency of CNN is exploited to handle the thermal and flicker noise of MS-N. A system-level analysis using a cohesive circuit-algorithmic framework on MNIST and CIFAR-10 datasets demonstrate an increase of 3% in worst-case classification error for MNIST when the integrated noise power in the bandwidth is ~ 1 µV 2 .

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“…Mobile terminals that operate on batteries, such as cellular phones, laptops, and tablets, the functionality of the devices depend on the kind of signal processing algorithm that gives more reliable performance with better power efficiency [1]. For mobile devices with limited battery power, replacing digital circuits with low-power analog circuits can improve the power efficiency of the devices significantly [6] [7]. Digital designs of Viterbi decoder have reached speed bottlenecks, as they are iterative; complexities in Add-Compare-Select (ACS) operation [4] have further restricted the improvement in operating frequency.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Architecture for OFDM with Optimized Design of Analog Viterbi Decoder

Cyril¹,

Varugheese²

2012

IJCA

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Analog Viterbi Decoder (AVD) is used for decoding of message from the received signal. Very recently mixed signal architecture for OFDM was proposed, that uses FFT processing in the analog domain. In this work, we propose a modified analog Viterbi decoder that performs decoding in analog domain. The proposed analog Viterbi decoder can be used in the mixed signal architecture of OFDM model and hence the proposed architecture is called as Hybrid OFDM architecture. Software reference model of the proposed AVD is developed using Simulink and is verified for its functionality. The Branch Metric Unit (BMU) and the adder unit that forms the subsystems of AVD are optimized for area, power and speed by designing the adders with 24 transistors. The schematic and layout is designed using Virtuoso targeting 130nm technology, the captured design is verified for its functionality using known test vector. A digital Viterbi decoder is also designed with same specifications as that of AVD, and is synthesized using Design Compiler for comparison. From the results obtained it is found that the AVD is 100 time faster, occupies 8 time less are and consumes power less than 86 micro W compared with digital decoder. The proposed AVD is suitable for low power and high speed applications and can be used in Hybrid OFDM architecture.

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A 531 nW/MHz, 128×32 current-mode programmable analog vector-matrix multiplier with over two decades of linearity

Cited by 31 publications

References 10 publications

A 256×256 separable transform CMOS imager

A 256×256 separable transform CMOS imager

An Energy-Efficient Mixed-Signal Neuron for Inherently Error-Resilient Neuromorphic Systems

Hybrid Architecture for OFDM with Optimized Design of Analog Viterbi Decoder

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