A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100&amp;#x003BC;A Cell Write Current

Hanzawa, S.; Kitai, N.; Osada, Kensuke; Kotabe, Akira; Matsui, Yasuhiro; Matsuzaki, N.; Takaura, N.; Moniwa, Masahiro; Kawahara, Takayuki

doi:10.1109/isscc.2007.373500

Cited by 31 publications

(31 citation statements)

References 4 publications

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“…The read voltage is set sufficiently high to invoke a sensible current but low enough to avoid write disturbance. Usually, the read voltage is clamped between 0.2V to 0.4V [11]. Similar to traditional memories, the word line connected to the gate of the access transistor is activated to read values from PCRAM cells.…”

Section: Pcram Backgourndmentioning

confidence: 99%

“…For SET operation, a moderate current pulse is applied for a longer duration to heat the cell above the GST crystallization temperature but below the melting temperature; for REST operation, a high power pulse heats the memory cell above the GST melting temperature. Recent PCRAM prototype chips demonstrate that the RESET latency can be as fast as 100ns and the peak SET current can be as low as 100µA [11,12].…”

Section: Pcram Backgourndmentioning

confidence: 99%

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Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Dong

Muralimanohar

Jouppi

et al. 2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

124

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The scalability of future massively parallel processing (MPP) systems is being severely challenged by high failure rates. Current hard disk drive (HDD) checkpointing results in overhead of 25% or more at the petascale. With a direct correlation between checkpoint frequencies and node counts, novel techniques that can take more frequent checkpoints with minimum overhead are critical to implement a reliable exascale system. In this work, we leverage the upcoming Phase-Change Random Access Memory (PCRAM) technology and propose a hybrid local/global checkpointing mechanism.After a thorough analysis of MPP systems failure rates and failure sources, we propose three variants of PCRAM-based hybrid checkpointing schemes, DIMM+HDD, DIMM+DIMM, and 3D+3D, which reduce the checkpoint overhead and offer a smooth transition from the conventional pure HDD checkpoint to the ideal 3D PCRAM mechanism. The proposed pure 3D PCRAM-based mechanism can ultimately take checkpoints with overhead less than 4% on a projected exascale system.

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Section: Pcram Backgourndmentioning

confidence: 99%

Section: Pcram Backgourndmentioning

confidence: 99%

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Dong

Muralimanohar

Jouppi

et al. 2009

Proceedings of the Conference on High Performance Computing Networking, Storage and Analysis

124

View full text Add to dashboard Cite

show abstract

“…V bg is the bandgap voltage. The proposed method uses one voltage (V clamp ) to generate I refnew and I read , which is different from previous methods which use two different voltages/circuits to generate I read and I ref [6,7,8]. In the proposed method, I refnew and I read are more likely to have a similar variation trend.…”

Section: Proposed Read Methodsmentioning

confidence: 95%

“…In the reference side, there are one selected cell, n À 1 unselected cells, one selected RTG and m À 1 unselected RTGs; in the array, there are also one selected cell, n À 1 unselected cells, one selected RTG and m À 1 unselected RTGs. Different from the conventional methods which use a constant reference current [6,7], the reference cell and the selected cell have the same parasitic elements in the proposed method. Fig.…”

Section: Proposed Read Methodsmentioning

confidence: 99%

Enhanced read performance for phase change memory using a reference column

Lei

Chen

et al. 2017

IEICE Electron. Express

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A reference column is employed to improve the read performance of phase change memory (PCM). In this way, a changeable reference current replaces the constant one; both the reference cell and the selected cell have the same bit line (BL) parasitic parameters and read transmission gate parasitic parameters in the read operation. Simulated in a 40 nm CMOS process, read access time of 4-Mb PCM is 30.65 ns with 190.9 ns improvement. Monte Carlo simulations show a 80.5 ns worst read access time compared to the conventional 1.58 µs.

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“…This power limit is mainly due to poor efficiency of the charge pump circuits [32], and typically leads to multiple write slots if the number of bit flips in a memory block is high. For instance, a PCM chip with 2-16 concurrent bit writes was produced in 90nm technology [51], and Samsung demonstrated a 20nm PCM chip that supports 128-256 concurrent bit writes [20].…”

Section: Performance Overheadmentioning

confidence: 99%

Architectural support for designing dependable non-volatile main memories

Tavana¹

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A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current

Cited by 31 publications

References 4 publications

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems

Enhanced read performance for phase change memory using a reference column

Architectural support for designing dependable non-volatile main memories

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