A 5 volt only 16M bit flash EEPROM cell with a simple stacked gate structure

A study of gateless OTP cell using a 45nm CMOS compatible process

“…The program gate disturb on unselected bit-line is unlikely to happen since the unselected bit-line voltage is zero. The program drain disturb is a design issue in common stacked gate memories due to FN tunneling between the drain and the charged floating gate [20]. In the gateless OTP cell, however, on the unselected wordline, the select transistor turns off and prevents the bit-line voltage from passing into the gateless storage node.…”

“…11 presents the read disturb of a gateless OTP cell. The 1/E model is utilized to predict the lifetime [20]. It reveals that at V D < À1.79 V, the fresh gateless OTP cell can sustain continuous read stresses for well over 10 years with a read current of no more than 0.1 lA.…”

Source-side injection single-polysilicon split-gate flash memory

“…Therefore, this approach can simplify the circuit organization as compared with the erase schemes used for STD-NOR. [25][26][27] Furthermore, since program and erase occur over different areas of the memory cell, the stresses of program and erase are spread over different regions, resulting in improved reliability, as will be evaluated in Sect. 5.2.…”

“…Soft write lifetime is defined as the DC stress time (t st ) that induces a V th,mg shift of 0.1 V. A 10-year lifetime, which is predicted by the extrapolation of slope of soft write lifetime vs 1/V d , can be guaranteed at a V d less than 3.5 V. It is clear that the S4-NOR cell can satisfy a higher soft write immunity than the STD-NOR cell. [25][26][27]37) This is because of the large reduction in the lateral field in the gap region during read-out operation as discussed in Sects. 3.3 and 4.1.…”