A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration

Ko, Chi-Tung; Pun, Kong-Pang; Gothenberg, A.

doi:10.1016/j.mejo.2015.06.016

Cited by 12 publications

(4 citation statements)

References 26 publications

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“…Time-to-Digital Converters (TDC) are devices used to convert the difference between the arrival time of two signals to a digital value [1], [2]. TDCs have long been used in physics experiments for Time-of-Flight (TOF) measurements, and laser range finders [1]- [5]. Lately, TDCs are becoming more popular and its range of applications has been growing.…”

Section: Introductionmentioning

confidence: 99%

“…The main performance figures of a TDC are resolution, differential non-linearity (DNL), and integral non-linearity (INL) [6]. Recently, some research works have reported resolutions under 10ps with DNL and INL under ±1 LSB [1], [3]. Perktold and Christiansen [3], claims to be the first to achieve a single-shot precision of 3 ps-rms.…”

Section: Introductionmentioning

confidence: 99%

“…Perktold and Christiansen [3], claims to be the first to achieve a single-shot precision of 3 ps-rms. The research work by Ko et al [1], proposes a Vernier sub-ranging TDC with DNL calibration, achieving a 5 ps resolution. A more recent work [2] presents a hybrid architecture TDC based on residual time extraction and amplification.…”

Section: Introductionmentioning

confidence: 99%

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All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

2019

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Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18um CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

2019

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“…In this TDC, resolution is equal to delay of each buffer, which is the long delay. To enhance resolution, Vernier delay line structure was used . The structure of this TDC is shown in Figure .…”

Section: Introductionmentioning

confidence: 99%

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

Razmdideh

Saneei

2018

Circuit Theory & Apps

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In this paper, a low-power and high-resolution latch-based time-to-digital converter (TDC) based on a multistage scheme is proposed. The proposed multistage TDC includes coarse, middle, and fine stages. The coarse stage is a new design of the flash TDC that is implemented by latches without using the delay cell. Also, the middle stage is a new design of the Vernier TDC with employed latches. The fine stage comprises parallel latches with different input loads.KEYWORDS high resolution, low power, TDC, VLSI | INTRODUCTIONHigh-precision time interval measurement is highly significant in many systems. Time-to-digital converter (TDC) is a system of time measurement, which converts the interval between 2 input pulses into a digital code. Time-to-digital converter has numerous applications, such as phase failure detection in the design of phase-locked loops. 1-5 The use of TDCs instead of phase comparator in phase-locked loop structure leads to removal of analog parts such as charge pump and loop filter. In addition, TDC is used in the structure of time-based analog to digital converters. 6,7 In this type of analog-to-digital converters, analog input voltage is turned into a time interval, and then the time interval is converted to a digital code through TDC. Also, TDC is used in medical imaging systems such as scanners, 8-11 other time of flight measurement methods, 12-14 and coupled with single photon avalanche diode array to build complementary metal oxide semiconductor image sensor. [15][16][17] A basic structure in design of TDC is flash TDC, which is composed of a delay line with several stages of buffers and comparators. 18 In this TDC, resolution is equal to delay of each buffer, which is the long delay. To enhance resolution, Vernier delay line structure was used. 19 The structure of this TDC is shown in Figure 1. This TDC is made up of several stages; each stage includes 2 different delay lines and a comparator. Resolution can be less than the delay of a buffer (resolution equivalent of difference in delay of 2 delay cells). In this structure, dynamic range is limited to the number of stages, and by adding extra stages, the dynamic range is increased. Because each stage is made up of 2 buffers and a comparator, power consumption of the circuit increases significantly. In addition, its linearity reduces as the number of stages increases. Two-dimensional Vernier TDC proposed in Vercesi et al 2 reduced the length of the delay lines to increase the efficiency compared with Vernier delay line TDC. However, this TDC had limited dynamic range and had serious problem in linearity. Three-dimensional Vernier space TDC 12 was introduced to increase dynamic range with minimizing the delay line. Vernier Ring TDC proposed in Yu et al 1 places the Vernier delay cells and arbiters in a ring format and reuses them for the measurement of the input time interval. This TDC achieves larger detectable range and fine time resolution, but has higher power consumption. Gated-Vernier TDC, which has 2 gated ring oscillators, acts as the...

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A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems

Sahani

Singh

Agarwal

2019

Advances in Intelligent Systems and Computing

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A 5-ps Vernier sub-ranging time-to-digital converter with DNL calibration

Cited by 12 publications

References 26 publications

All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

Low‐power, latch‐based multistage time‐to‐digital converter in 65 nm CMOS technology

A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems

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