A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

Fang, Jie; Thirunakkarasu, Shankar; Yu, Xuefeng; Silva-Rivas, Fabian; Zhang, Chaoming; Singor, Frank; Abraham, Jacob A.

doi:10.1109/tcsi.2017.2661481

Cited by 53 publications

(21 citation statements)

References 16 publications

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“…The throughput of a PWB is around 5 GS/s. The DACs [33] and ADCs [34] both operate at 5 GS/s and support to 7-bits. The GDDR6 SDRAM operates at 16 G with a 256-bit bus size [35].…”

Section: V2 Deap Performancementioning

confidence: 99%

Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)

Bangari

Márquez

Miller

et al. 2020

IEEE J. Select. Topics Quantum Electron.

157

112

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Convolutional Neural Networks (CNNs) are powerful and highly ubiquitous tools for extracting features from large datasets for applications such as computer vision and natural language processing. However, a convolution is a computationally expensive operation in digital electronics. In contrast, neuromorphic photonic systems, which have experienced a recent surge of interest over the last few years, propose higher bandwidth and energy efficiencies for neural network training and inference. Neuromorphic photonics exploits the advantages of optical electronics, including the ease of analog processing, and busing multiple signals on a single waveguide at the speed of light. Here, we propose a Digital Electronic and Analog Photonic (DEAP) CNN hardware architecture that has potential to be 2.8 to 14 times faster while maintaining the same power usage of current state-of-the-art GPUs.

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“…The throughput of a PWB is around 5 GS/s. The DACs [33] and ADCs [34] both operate at 5 GS/s and support to 7-bits. The GDDR6 SDRAM operates at 16 G with a 256-bit bus size [35].…”

Section: V2 Deap Performancementioning

confidence: 99%

Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)

Bangari

Márquez

Miller

et al. 2020

IEEE J. Select. Topics Quantum Electron.

157

112

View full text Add to dashboard Cite

show abstract

“…In TIADC systems, channel mismatches seriously degrade the signalto-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) [18,19,20,21,22,23,24,25,26,27,28,29]. In published literature, studies of TIADC are based on the effects of channel mismatches on the spectrum or dynamic performance such as SNDR and SFDR [14,16,17,18,19,20,21,22,23,24,25,26,27,29,30,31,32]. Under the condition of large bandwidth, it is impossible to eliminate channel mismatches completely.…”

Section: Introductionmentioning

confidence: 99%

Analysis of TIADC channel mismatch effects on high-resolution range profile

Xiao

Zhang

2020

IEICE Electron. Express

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The wideband echo signals of the imaging radar can be processed by pulse compression to obtain high-resolution range profile (HRRP). The resolution of HRRP is proportional to the signal bandwidth. The pursuit of high resolution makes the bandwidth of radar transmitting signal larger and larger. And the corresponding sampling rate of receiver becomes so high that analog-to-digital conversion cannot be realized by a single chip correctly. Time-interleaved analog-to-digital converter (TIADC) technique increases sampling rate of radar receiver, but channel mismatches are brought in. Channel mismatches significantly deteriorate the dynamic performance of radar receiver. Effects of channel mismatch on SNR, SNDR and SFDR are studied in previous literatures. Derivation and simulation of TIADC channel mismatch effecting on HRRP are performed in this letter. Simulation results show that without considering the amplitude-frequency distortion and phase-frequency distortions of the radar system, when the gain mismatch is less than 0.7 times and the clock mismatch is less than 0.25 rad, the influence of the channel mismatch on the HRRP can be neglected. The results provide a reference for system design and compensation method, which are useful for the designer to determine whether complex channel mismatch calibration is necessary under specific application background.

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“…In recent years, with the improvement of CMOS technology, successive approximation register (SAR) analog-todigital converters ADCs have been able to achieve sampling rates of several hundreds of MS/s with high power efficiency and small area [1,2,3,4,5,6,7,8,9,10]. Meanwhile, 8 to 12-bit SAR ADCs could reach sampling rates of hundreds or thousands MS/s and provide compact area and outstanding power efficiency [11,12,13,14,15,16,17,18,19,20,21,22].…”

Section: Introductionmentioning

confidence: 99%

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Pu-Jie

et al. 2019

IEICE Electron. Express

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A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

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A 5-GS/s 10-b 76-mW Time-Interleaved SAR ADC in 28 nm CMOS

Cited by 53 publications

References 16 publications

Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)

Digital Electronics and Analog Photonics for Convolutional Neural Networks (DEAP-CNNs)

Analysis of TIADC channel mismatch effects on high-resolution range profile

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

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