A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique

Abstract

A 12-bit 100-MS/s 83 dB SFDR SAR ADC with sampling switch linearity enhanced technique is proposed. With the variation of input signals, the parasitic capacitance variation of sampling switch is reduced and the total parasitic capacitance is also depressed. Moreover, with substrate boost technique, the on-impedance of sampling switch would decrease. To demonstrate the proposed technique, a design of 12bit 100-MS/s SAR ADC is fabricated in 40-nm CMOS technology, consuming 2 mW from 1 V power supply with a SNDR >65 dB and SFDR >83 dB. The proposed ADC core occupies an active area of 0.02 mm 2 , and the corresponding FoM is 13.8 fJ/conversion-step with Nyquist frequency.

A 10-bit 120MS/s SAR ADC using tri-switch sampling and VCM-stable switching scheme in 40-nm CMOS

“…Each owns specific characteristics in terms of sample rate, accuracy, etc. Featuring high power efficiency and low circuit complexity, asynchronous charge-redistributed SAR ADCs have become a popular choice for moderate-resolution and moderate-speed applications [16,17,18,19,20,21,22,23,24,25]. The monotonic switching scheme and top-plate sampling proposed in [16] dramatically reduce the average switching power and total capacitance.…”

A high-speed low-power SAR ADC in 40nm CMOS with combined energy-efficient techniques

“…In the past days, the conversion rate of SAR ADC is limited and the pipelined ADC [1][2][3][4][5] is the mainstream architecture. With the scaling down of the transistor size, the single-channel SAR ADCs [6][7][8][9][10] can achieve hundreds of MS/s sampling rate with resolution no less than 10bit. Meanwhile, the hybrid structure pipelined SARs [11][12][13] are popular to realize the high-speed mediumresolution ADC.…”