A 5-bit 5 Gs/s flash ADC using multiplexer-based decoder

Abstract

This paper presents a 5-bit flash analog-to-digital converter design using the 0.18-µ m Taiwan Semiconductor Manufacturing Company's CMOS technology library. The designed system consists of 2 main blocks, a comparator array, and a digital decoder. The digital decoder contains a latch, 1-of-N decoder, and fat-tree encoder units. The 1-of-N decoder is implemented using 2 × 1 multiplexers. As a result, the active die area and the power consumption are reduced, in addition to an increase in the sampling frequency. The power supply voltage range for the overall system is ± 0.9 V. For testing purposes, a ramp signal of between -0.45 V and 0.7 V is applied to the converter input. The sampling frequency is 5 Gs/s. The simulation results include a maximum power consumption of 28 mW, integral nonlinearity values of between -0.65 least significant bits (LSB) and + 0.01 LSB, differential nonlinearity values of between -0.3 LSB and + 0.13 LSB, and an active die area of 0.1 mm 2 .

A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

“…The aspect ratios of the mosfets and the critical bias voltage values are listed in Table 1. The power supply voltage for the comparator is ±1.5 V. This circuit is basically a differential pair input comparator circuit, which was also used in the authors earlier work [32] with different design parameters adapted to 0.18 µm CMOS technology. In addition to comparator in stage (M0, M1, M2, M3, M5, M6), the voltage gain is boosted by a common source amplifier (M8) and a CMOS inverter stage (M11, M12) at the output.…”

“…Depending on the clock signal, either the logic value of former input signal is kept at the output or the logic value of current input signal is transmitted to the next stage of the ADC. Thus, digital part of the ADC is somehow relaxed for accurate conversion, because of continuous change of the analog input signal [32,33]. In other words, when the clock signal is logic "0", it means that the analog input is sampled at this time; however, when the clock signal is logic "1" it means that the digital conversion of that sample is executed in the digital part of the converter.…”

Darlington CMOS İnverter Tabanlı Paralel Analog-Sayısal Dönüştürücü Tasarımı

“…Darlington cmos inverter tabanlı karşılaştırıcı bloğu dc sonuçları.2.2 Sayısal Kod Çözme Bloğu ( Digital Encoder Block)Sayısal kod çözme bloğu; dinamik tutucu devresi, 1-n kodlayıcı ve pla-rom bloğundan oluşmaktadır. A/S dönüştürücü tasarımlarında analog ve sayısal bloklar arasında ki kontrolü sağlamak için dinamik tutucu devresine ihtiyaç vardır [10,29]…”