A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

Lin, Ying-Zu; Lin, Cheng-Wu; Chang, Soon-Jyh

doi:10.1109/tvlsi.2009.2013628

Cited by 42 publications

(16 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The results include the actual location of offset in (8) (dotted curves off 1,1 and off 2,4 ) and the corresponding calibration code C j . They also depict the initial uncalibrated offset off i,j [0] (lines with square markers) and the adaptive measurement (OFF 1,1 and OFF 2,4 ), evaluated from (6). Notice that the proposed technique has a very fast response even when two stages are calibrated simultaneously.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…does not change and ENABCCG = 0. n (6) where  = 2 -m (with m integer) is the adaptive constant step in the example, ENABCCG is a control signal which enables (logical value '1') or disables (logical value '0') the next CCG operation, and j is the updating pointer which determines the specific calibration code C j that must be updated. If k reaches an extreme value, 0 or M, only one decision of (6) applies.…”

Section: A Offset Estimationmentioning

confidence: 99%

“…The task of calibration block CCG is to determine the value of C j. The generation of C j is performed straightforward in the digital domain using the offset estimation OFF j derived in (6). Starting from an initial value of zero, C j is modified to ensure that OFF j remains low enough.…”

Section: Calibration Code Generationmentioning

confidence: 99%

“…Actually, the huge variability of SA-DLCs limits their use to low-resolution stages, typically of 1.5 bits. Practical stage implementations with higher resolution consider comparator topologies based on a front-end preamplifier [5], they rely on relatively complex correction techniques in the analog domain [6] and/or they add extra clock phases [7]. In these solutions, the power optimization of the complete Pipeline ADC needs to consider significant constrains between Manuscript received July 18, 2013.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Ginés

Peralías

Rueda

2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-This paper presents a low-cost digital technique for background calibration of comparator offsets in Pipeline ADCs. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power highspeed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

Section: A Offset Estimationmentioning

confidence: 99%

Section: Calibration Code Generationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Ginés

Peralías

Rueda

2015

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

show abstract

“…Because of increasing usage of digital signal processing, wireless communication systems and broadband systems, the demands for low resolution and high speed fully parallel A/D Converters are increasing [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Aytar

2015

Journal of Electrical Engineering

View full text Add to dashboard Cite

This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 µm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are ( 0/ + 0.63 ) LSB and ( −0.26/ + 0.31 ) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

show abstract

Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

Ginés

Peralías

Aledo

et al. 2019

Circuit Theory & Apps

View full text Add to dashboard Cite

Summary This paper presents a fast background calibration method for comparator offsets in pipeline ADCs and analyzes the practical considerations in a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐Signal‐to‐noise plus Distortion Ratio [SNDR]). A self‐repairing (SR) thermometer‐to‐binary encoder is developed to deal with malfunctioning in presence of high comparator offsets greater than one‐half least‐significant bit (LSB). In this situation, the effective thresholds between two adjacent comparators could be inverted leading to a faulty behavior with conventional architectures. The proposed solution allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed. As demonstrator, its application to a 15‐bit pipeline ADC using a novel calibrated dynamic‐latch comparator (DLC) with internal threshold reference generation and no preamplifier is presented, showing a reduction on the total power consumption of 22% with respect to a design without calibration targeting the same specifications.

show abstract

A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme

Cited by 42 publications

References 5 publications

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

Contact Info

Product

Resources

About