Background Digital Calibration of Comparator Offsets in Pipeline ADCs

Abstract

Abstract-This paper presents a low-cost digital technique for background calibration of comparator offsets in Pipeline ADCs. Thanks to calibration, comparator offset errors above half the stage least-significant bit (LSB) margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power highspeed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the Pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

Fast adaptive comparator offset calibration in pipeline ADC with self‐repairing thermometer to binary encoder

“…Although the proposed calibration is based in our previous work, the key improvement here is found precisely in this adaptive assignment. For the sake of simplicity, the stage index “ i ” will be here implicitly assumed.…”

“…Giving the importance of calibration time, the research in reducing the number of samples to achieve convergence has been an active topic in the calibration context . In Ginés, Peralías, and Rueda, a low‐cost digital technique for background calibration of comparator offsets in pipeline ADCs was proposed at algorithmic level, which reduces convergence time in several orders of magnitude.…”

“…The proposed calibration technique allows a dynamic assignment of the calibration code associated to each comparator improving convergence speed when transition inversions occur (at least 60% less samples are required in a worst‐case situation with minimum inversion). The validation of the algorithm is done in this paper using behavioral simulations as in Ginés, Peralías, and Rueda but also using a CMOS demonstrator as an additional novelty. We will analyze the practical considerations in the technique implementation to a 1.8 V 0.18 μm 100Msps pipeline ADC with 15‐bit resolution (74 dB‐SNDR), including a circuit‐level implementation of the subADC comparators based on a novel calibrated DLC without front‐end preamplification and without resistor ladder for threshold generation.…”

Closed-loop simulation method for evaluation of static offset in discrete-time comparators

“…6a-b, respectively, which are comprised by: 1) a high-precision comparator based on a switched capacitor front-end with preamplifer, a dynamic latch followed by a RS latch and buffers, and 2) a relatively low-accuracy comparator without active front-end, the input of which is directly a stand-alonealone dynamic latch (SADL), respectively. In the first stage, threshold voltages (l p ,l n ) are generated from a resistive ladder (omitted in the figure), while in the second topology, its generation is embedded in the circuit considering a size imbalance between input transistors M R1-R2 [2] (in both examples, zero ideal thresholds, l ideal = 0, were implemented). Fig.…”

“…Their amplitudes have to span (with enough security margin) the maximum and minimum expected threshold shift, which implies long transient simulations during verification, affecting to the design productivity. For instance, dynamic latch comparators could suffer offset errors up to 200mV in CMOS technologies [1]- [2], and hence, a range of 400mV would be required (span = 400mV). In these conditions, reaching a 1mV precision during PVT variation characterization (accuracy = 1mV) would need 400 cycles (=span/accuracy) per simulation run.…”