A 5.8 GHz Adaptive CMOS Image Rejection Mixer for DSRC Transceiver

Bai, Zeqing; Kim, Sung Jin; Rad, Reza; Lee, Kang-Yoon

doi:10.1109/iceic49074.2020.9051172

Cited by 3 publications

(4 citation statements)

References 3 publications

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“…linearity. To evaluate the overall performance of the proposed ADC, the commonly used parameter, Figure of Merit (FOM), is used as FOM = P ADC min{F S , 2 × ERBW}2 ENOB (4) where, F S denotes the sampling rate and P ADC is the power consumed by the structure.…”

Section: Resultsmentioning

confidence: 99%

“…It satisfies the aforementioned requirements without any externally connected block like low-noise amplifier (LNA) and external power amplifier (PA) [ 3 ]. The main building blocks consists of a matching network (M.N), single pole double throw (SPDT) switch, an inductively generated low-noise amplifier (LNA) to amplify the input signal, a mixer (MIXER), a 12-bit ADC, a 12-bit DAC, a received signal strength indicator (RSSI), a variable gain amplifier (VGA) with a low pass filter (LPF) and power amplifier (PA) [ 4 ]. An integrated SAR ADC allows transceiver to communicate with the digital baseband [ 5 ].…”

Section: Introductionmentioning

confidence: 99%

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

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A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Shehzad

Verma

Khan

et al. 2021

Sensors

Self Cite

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“…Recently, the new Electronic Toll This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ Collection (ETC) system has also been switched to 5.8 GHz band [3][4][5][6][7][8][9]. Using DSRC is principal for an ETC system when it is about a two-way wireless communication between the Onboard Units (OBUs) and the Roadside Units (RSUs).…”

Section: Introductionmentioning

confidence: 99%

A 5.8 GHz RF Receiver Front-End with 77.6 dB Dynamic Range AGC for a DSRC Transceiver

et al. 2022

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“…Figure 1 depicts the top block diagram of the DSRC receiver system, which consists of a low-noise amplifier (LNA), a mixer (MIXER), a band-pass filter (BPF), a received signal strength indicator (RSSI) circuit with a 10-bit ADC, and a programmable gain amplifier (PGA). The BPF is inserted between the PGA and MIXER so that the spur and out-of-band noise, such as the DC offset at low frequency and flicker noise before the in-band is passed into the PGA, and the adjacent-channel signals at signals at high frequency can be removed [3][4][5]. According to the detected signal strength, it is important to maintain the gain of each block in the receiver to maintain an appropriate signal level into the ADC.…”

Section: Introductionmentioning

confidence: 99%

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

et al. 2020

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A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, and an effective number of bits (ENOB) of 9.74 bits with a sampling rate of 1 MS/s at measurement levels. The implemented SAR ADC consumes 14.8 µW power at 1 V power supply.

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A 5.8 GHz Adaptive CMOS Image Rejection Mixer for DSRC Transceiver

Cited by 3 publications

References 3 publications

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

A 5.8 GHz RF Receiver Front-End with 77.6 dB Dynamic Range AGC for a DSRC Transceiver

A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application

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