A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Sai, Akihide; Okuni, Hidenori; Ta, Tuan Thanh; Kondo, Satoshi; Tokairin, Takashi; Furuta, Mamoru; Itakura, Tetsuro

doi:10.1109/jssc.2016.2603993

Cited by 21 publications

(11 citation statements)

References 10 publications

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“…Akihide Sai et al proposed a hybrid-loop receiver structure based on ADPLL [36]. The Time to Digital converter will improve the receiver dynamic range.…”

Section: Adpll For Iot and Ble Applicationsmentioning

confidence: 99%

An analysis of ADPLL applications in various fields

Rai¹,

Marimuthu²

2020

IJEECS

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<span>ADPLL is now an essential component in applications like wireless sensor networks, Internet of things, health care applications, agricultural applications, etc, and also due the requirement of digital implementation by the industries. ADPLL consists of a phase detector, loop filter and digital controlled oscillator. The conventional PLL and digital PLL used for frequency synthesis, clock recovery circuit and synchronization give imprecise performance with respect to reliability, speed, power consumption, noise, locking speed, cost, etc. ADPLL overcomes the drawbacks of conventional PLL and digital PLL. In this paper, different approaches followed in All Digital Phase Locked Loop (ADPLL) for various applications are reviewed and their performance is compared based on components, modulation functions, frequency range, power utilization etc. In addition, an ADPLL with wide tuning range and frequency resolution is designed and implemented using automatic placement and routing, time to digital converter, digital loop filter and ring based oscillator. The ADPLL outputs and the results are analyzed with micro wind tool. The design gives a frequency range from 1.0-5.5GHz with low power consumption and it can also be used for Clock generation applications. </span>

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“…Akihide Sai et al proposed a hybrid-loop receiver structure based on ADPLL [36]. The Time to Digital converter will improve the receiver dynamic range.…”

Section: Adpll For Iot and Ble Applicationsmentioning

confidence: 99%

An analysis of ADPLL applications in various fields

Rai¹,

Marimuthu²

2020

IJEECS

View full text Add to dashboard Cite

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“…As a result, the dynamic-range of the DPLL-based ADC is greatly degraded due to the open-loop operation. For achieving better V2F linearity, a varactor array can be implemented with resistor-interpolated voltage biases [8]. Sixteen varactor banks are used to achieve a K VCO of 800 kHz/V, which consumes a large chip area and produces the large parasitic capacitance of the LC oscillator.…”

Section: A Dpll-based Adc With Dynamic Range Enhancementmentioning

confidence: 99%

“…Conflicts will occur if both loops have comparable BW. Analysis in [8] shows that the DPLL with a wider BW than that of the LPF can properly stabilize two loops, i.e., a stabilized f RX,LO can be realized. However, excessively increasing the BW of the DPLL will decrease the stability of the DPLL due to the limited sampling frequency and the loop latency.…”

Section: A Dpll-based Adc With Dynamic Range Enhancementmentioning

confidence: 99%

“…Sliding-IF (SIF) is another popular architecture for low-power design, although this architecture causes severe image problems [4]- [7]. Reference [8] proposed a hybrid-loop RX to improve the blocker tolerance from the SIF phaseto-digital converter (SIF-PDC) architecture [4]. In order to realize single-path downconversion demodulation, the GFSK constellation is transformed into a differential phase-shift keying (DPSK) constellation at the RX mixer output by shifting the RX local oscillator (LO) frequency by 250 kHz from its carrier frequency [8].…”

mentioning

confidence: 99%

“…Reference [8] proposed a hybrid-loop RX to improve the blocker tolerance from the SIF phaseto-digital converter (SIF-PDC) architecture [4]. In order to realize single-path downconversion demodulation, the GFSK constellation is transformed into a differential phase-shift keying (DPSK) constellation at the RX mixer output by shifting the RX local oscillator (LO) frequency by 250 kHz from its carrier frequency [8]. A digital phase-locked loop (DPLL) is used as an LO, and an analog-to-digital converter (ADC) is used to digitize the analog-baseband (ABB) data from the ADC path, as shown in Fig.…”

mentioning

confidence: 99%

See 2 more Smart Citations

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Liu

Sun

Tang

et al. 2018

IEEE J. Solid-State Circuits

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This paper presents a Bluetooth low-energy (BLE) transceiver (TRX) achieving ultra-low-power operation for Internet-of-Things (IoT) applications. The proposed TRX utilizes a wide-bandwidth low-power fractional-N digital phase-locked loop (DPLL) as a central component to perform multiple roles: a direct frequency modulator for the transmitter (TX), an analogto-digital converter (ADC) for the receiver (RX), a local oscillator for RX, and a frequency and phase synchronizer for the RX. The DPLL-based single-path downconversion method is adapted to halve the analog baseband circuit to further reduce the power consumption while maintaining a high interference rejection. A DPLL-based ADC with a digital-to-analog converter feedback greatly improves the ADC dynamic range, which improves the RX sensitivity and interference tolerance. By maximally reducing the required radio frequency and analog front-end components in RX, an RX power consumption of 2.3 mW is achieved with a −94 dBm sensitivity. The RX also satisfied all interference requirements with a certain margin. A 5.0-mW TX is achieved when delivering an output power of 0 dBm with a frequency-shift keying error of only 1.89%.

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Ultra-Low Power Receivers for IoT Applications: A Review

Wcntzloff

Alghaihab

2020

2020 IEEE Custom Integrated Circuits Conference (CICC)

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A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Cited by 21 publications

References 10 publications

An analysis of ADPLL applications in various fields

An analysis of ADPLL applications in various fields

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Ultra-Low Power Receivers for IoT Applications: A Review

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