A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture

Mochida, Reiji; Kouno, Kazuyuki; Hayata, Yuriko; Nakayama, Masayoshi; Ono, Takashi; Suwa, Hitoshi; Yasuhara, Ryo; Kawasaki, Koji; Mikawa, Takumi; Gohou, Y.

doi:10.1109/vlsit.2018.8510676

Cited by 157 publications

(77 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In recent years, many ReRAM-based CIM chips have been proposed, with attempts made to balance between accuracy and efficiency while achieving higher precision. A trend to increase the number of I/O and precision of weights has been observed for operations ranging from 1b-input, ternaryweight, 3b-output [3] and 1b-input, 8b-weight, 1b-output [4] to 2b-input, 3b-weight, 4b-output [5] (see Fig. 1).…”

Section: Reram-based Cimmentioning

confidence: 89%

“…The other method involves making a multilevel cell (MLC) ReRAM to represent the weight value with more than one bit. In [4], a ReRAM with eight levels that achieve 256 times higher precision of weight is proposed. However, due to the process variation in ReRAM, precisely controlling the resistance of ReRAM with 256 levels is difficult.…”

Section: B Weight Limitationsmentioning

confidence: 99%

See 1 more Smart Citation

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Wei

Jhang

Chen

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

Nonvolatile computing-in-memory (nvCIM) exhibits high potential for neuromorphic computing involving massive parallel computations and for achieving high energy efficiency. nvCIM is especially suitable for deep neural networks, which are required to perform large amounts of matrix-vector multiplications. However, a comprehensive quantization algorithm has yet to be developed, which overcomes the hardware limitations of resistive random access memory (ReRAM)-based nvCIM, such as the number of I/O, word lines (WLs), and ADC outputs. In this article, we propose a quantization training method for compressing deep models. The method comprises three steps: input and weight quantization, ReRAM convolution (ReConv), and ADC quantization. ADC quantization optimizes the error sampling problem by using the Gumbel-softmax trick. Under a 4-bit ADC of nvCIM, the accuracy only decreases by 0.05% and 1.31% for the MNIST and CIFAR-10, respectively, compared with the corresponding accuracies obtained under an ideal ADC. The experimental results indicate that the proposed method is effective for compensating the hardware limitations of nvCIM macros. INDEX TERMS Compression, computing-in-memory (CIM), deep learning, quantization, resistive random access memory (ReRAM).

show abstract

Section: Reram-based Cimmentioning

confidence: 89%

Section: B Weight Limitationsmentioning

confidence: 99%

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Wei

Jhang

Chen

et al. 2020

IEEE J. Explor. Solid-State Comput. Devices Circuits

View full text Add to dashboard Cite

show abstract

“…Through using a cross-point array with only a single RRAM [53,54] or one-transistor and one-resistor (1T-1R) configuration, [55][56][57][58][59] diverse classification and recognition features and functions have been explored and demonstrated experimentally. A two-layer perceptron has been constructed by the building of 128 Â 64 Ta/HfO x /Pt (from top to bottom) based 1T-1R arrays.…”

Section: Rrammentioning

confidence: 99%

“…Similar hardware performance was also verified through mass-produced Ta 2 O 5 /TaO x -based 1T-1R synapses. [59] The uniform analog states linearly tuned from 20 to 50 μA with a verification technique that allowed a maximum recognition accuracy of 90% on the MNIST database. The 180 nm Ta 2 O 5 /TaO x -based RRAM exhibited a similar number of synapses per unit area when compared with a 65 nm SRAM.…”

Section: Rrammentioning

confidence: 99%

Recent Advancements in Emerging Neuromorphic Device Technologies

Woo

Kim

et al. 2020

Advanced Intelligent Systems

View full text Add to dashboard Cite

The explosive growth of data and information has motivated technological developments in computing systems that utilize them for efficiently discovering patterns and gaining relevant insights. Inspired by the structure and functions of biological synapses and neurons in the brain, neural network algorithms that can realize highly parallel computations have been implemented on conventional silicon transistor‐based hardware. However, synapses composed of multiple transistors allow only binary information to be stored, and processing such digital states through complicated silicon neuron circuits makes low‐power and low‐latency computing difficult. Therefore, the attractiveness of the emerging memories and switches for synaptic and neuronal elements, respectively, in implementing neuromorphic systems, which are suitable for performing energy‐efficient cognitive functions and recognition, is discussed herein. Based on a literature survey, recent progress concerning memories shows that novel strategies related to materials and device engineering to mitigate challenges are presented to primarily achieve nonvolatile analog synaptic characteristics. Attempts to emulate the role of the neuron in various ways using compact switches and volatile memories are also discussed. It is hoped that this review will help direct future interdisciplinary research on device, circuit, and architecture levels of neuromorphic systems.

show abstract

“…Many ideas of PIMs have been proposed by using SRAM cells [18]- [20] or non-volatile memory (NVM) cells. Especially, NVM based PIMs with such as flash [21], [22], ReRAM [23], [24] or PCM [25], are expected to achieve extremely higher power efficiency thanks to massively parallel execution with multiple weights per cell and no data transfer from outside of the macro to load weigh information. Peripheral circuit design of PIM macros can be quite different from that of normal macros for conventional data storage.…”

Section: Processing-in-memory For E-aimentioning

confidence: 99%

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Kimura

Taito

Hidaka

2020

IEICE Trans. Electron.

View full text Add to dashboard Cite

Embedded system approaches to edge computing in IoT implementations are proposed and discussed. Rationales of edge computing and essential core capabilities for IoT data supply innovation are identified. Then, innovative roles and development of MCU and embedded flash memory are illustrated by technology and applications, expanding from CPS to big-data and nomadic/autonomous elements of IoT requirements. Conclusively, a technology roadmap construction specific to IoT is proposed.

show abstract

A 4M Synapses integrated Analog ReRAM based 66.5 TOPS/W Neural-Network Processor with Cell Current Controlled Writing and Flexible Network Architecture

Cited by 157 publications

References 1 publication

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

A Relaxed Quantization Training Method for Hardware Limitations of Resistive Random Access Memory (ReRAM)-Based Computing-in-Memory

Recent Advancements in Emerging Neuromorphic Device Technologies

Essential Roles, Challenges and Development of Embedded MCU Micro-Systems to Innovate Edge Computing for the IoT/AI Age

Contact Info

Product

Resources

About