A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications

Xing, Chen; Breiholz, Jacob; Yahya, Farah B.; Lukas, Christopher J.; Kim, Hun-Seok; Calhoun, Benton H.; Wentzloff, David D.

doi:10.1109/rfic.2018.8428960

Cited by 14 publications

(9 citation statements)

References 7 publications

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“…When transients in the type-II PLL settle and the SSPLL acquires phase-lock, any perturbations in the RVCO zero crossings (∆T RV CO ) due to the phase noise are converted into a non-zero voltage error (∆V samp ) by the SSPD. 1 Any small perturbation ∆T RV CO is converted into an error voltage given by ∆V samp = SR SSP D • ∆T RV CO (see Fig. 2), where SR SSP D is the slew rate of the RVCO output.…”

Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

“…The [7]. The high-pass filtered RVCO 1 Since a high frequency RVCO output has a very high slew rate (SR SSP D ), a high phase error detection gain is expected. phase noise at the SSPLL output Out RV CO undergoes further FPNC-based noise filtering (theoretical filtering upto f ref /2 cannot be reached due to the aliasing from sampling operation and filtering of the hold function in the SSPD [7]).…”

Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

“…Due to multiplication factor of N 2 , the added reference and DTC noise limit the final precision of FPNC-based RVCO phase noise cancellation. However, due to the ultra-low-power requirements of BLE radios [1], [2], the low-power RVCO noise can dominate both in-band and out-of-band PLL phase noise spectrum and can significantly benefit from the FPNC technique around 2.5 GHz carrier frequency range.…”

Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

“…Ring voltage-controlled oscillator (RVCO)-based phaselocked loops (PLLs) are gaining popularity for application in bluetooth low-energy (BLE) radios for frequency synthesis [1], [2]. The RVCOs occupy a smaller chip area, but suffer from poor phase noise performance compared to LC oscillators with same power consumption.…”

Section: Introductionmentioning

confidence: 99%

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Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Renukaswamy

Markulic

Wambacq

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and lowarea ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.Index Terms-Calibration, digital-to-time converter (DTC), frequency synthesis, phase-locked loop (PLL), phase noise cancellation, ring oscillator, sub-sampling PLL (SSPLL), voltagecontrolled delay line (VCDL).

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Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

Section: Fractional-n Sspll With Fpncmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Renukaswamy

Markulic

Wambacq

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…To lower the power consumption of the oscillator in a PLL, a ring oscillator can be used [11]. However, a ring oscillator has poor phase noise, and thus significantly degrades the PLL output swing in the current-limited region, in which the output swing V AMP is mainly limited by the tank impedance.…”

Section: A Transformer-based Stacked-g M Dcomentioning

confidence: 99%

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Liu

Shirane

Okada

et al. 2019

IEEE J. Solid-State Circuits

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This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265-µW ultra-lowpower operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked-g m oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional-N DPLL consumes only 265 µW while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB.

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Design Considerations of Frequency Modulated Ultralow Power Transmitter

Chen

Wentzloff

2022

Handbook of Biochips

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A 486 µW All-Digital Bluetooth Low Energy Transmitter with Ring Oscillator Based ADPLL for IoT applications

Cited by 14 publications

References 7 publications

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Design Considerations of Frequency Modulated Ultralow Power Transmitter

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