Fractional-N Sub-Sampling PLL Using a Calibrated Delay Line for Phase Noise Cancellation

Abstract

This work extends the concept of feedforward phase noise cancellation (FPNC) technique to a fractional-N subsampling phase-locked loop (SSPLL), using a low-power and lowarea ring voltage-controlled oscillator (RVCO). The sub-sampling phase detector is used to measure the RVCO phase noise and its output is used to tune the voltage-controlled delay line (VCDL), in order to cancel the excess phase noise measured. A background calibration algorithm is proposed to calibrate the gain error of the VCDL, which improves the phase noise cancellation accuracy. The system model simulations shows that, the total integrated phase noise of the 2.4 GHz fractional-N SSPLL improves from -20.6 dBc to -34 dBc after phase noise cancellation.Index Terms-Calibration, digital-to-time converter (DTC), frequency synthesis, phase-locked loop (PLL), phase noise cancellation, ring oscillator, sub-sampling PLL (SSPLL), voltagecontrolled delay line (VCDL).