A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect

Nicoletta, C.; Álvarez, José Marcos Alonso; Barkin, E.; Chao, Chai-Chin; Johnson, Bill; Lassandro, F.; Patel, Parth; Reid, Dan; Sanchez, H.; Seigel, J.; Snyder, M. R.; Sullivan, S.; Taylor, Scott A.; Vo, Minh

doi:10.1109/4.799852

Cited by 17 publications

(9 citation statements)

References 6 publications

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“…In the year, 2002, Nicoletta et al (the concept was proposed in 1999) [6] published a modified version of MESI protocol along with a new RISC architecture, and named it MERSI cache coherency protocol, which was mostly used in PowerPC G4 computers by Apple Inc. In this protocol, the state 'R' was introduced, which stands for Read only or Recent state, other than that all the other states are similar to MESI protocol.…”

Section: Recent Research and Advancement In Cache Coherency Protocolsmentioning

confidence: 99%

Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

Dey¹,

Nair²

2014

IJCA

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To improve the efficiency of a processor to work with data, cache memories are used to compensate the latency delay to access data from the main memory. But because of the installation of different caches in different processors in a shared memory architecture, makes it very difficult to maintain consistency between the cache memories of different processors. For that reason, having a cache coherency protocol is really essential in those kinds of system. There are different coherency protocols for caches to maintain consistency between different caches in a shared memory system. Few of the famous cache coherency protocols are MSI, MESI, MOSI, MOESI, MERSI, etc. In this paper, the primary focus were to study the working protocols of MESI (Modified-Exclusive-Shared-Invalid) and MOESI (ModifiedOwned-Exclusive-Shared-Invalid) cache coherency protocols by designing a simple cache simulator in java, and publish the results and research findings. The main purpose of this paper is to provide new researchers and computer science students the idea regarding how to build and implement a simulator in order to understand the novel cache coherency protocols.

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Section: Recent Research and Advancement In Cache Coherency Protocolsmentioning

confidence: 99%

Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

Dey¹,

Nair²

2014

IJCA

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“…CPU94: a 0.50 m dual-issue design with 4 pipeline stages [4], CPU99: a 0.20 m triple-issue design with 4 pipeline stages and two vector execution units [5], and, CPUO1: a 0.165 m quad-issue design with 7 pipeline stages.…”

Section: Estimating Frequency From Supply Voltagementioning

confidence: 99%

Compact models for estimating microprocessor frequency and power

Athas¹,

Youngs²,

Reinhart³

2002

Proceedings of the International Symposium on Low Power Electronics and Design

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This paper describes compact mathematical models for estimating the frequency performance and power dissipation of a microprocessor as a function of the supply voltage. The objective is to estimate the frequency and/or power performance across a wide range of supply voltages and operating frequencies using only a small number of configurable parameters and equations. These compact equations are amenable to hand calculations and spreadsheet manipulation. The configurable parameters are derived from actual measurements of microprocessor chips and are calculated using the least-squares curve-fitting method.

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“…Fig. 2 shows the measured frequency-voltage relationship for five recent microprocessors [5][6][7][8][9]. These chips are all power-limited based on the definition given above.…”

Section: Introductionmentioning

confidence: 99%

Optimal sequencing energy allocation for CMOS integrated systems

Saint-Laurent

Oklobdzija

Singh³

et al.

Proceedings International Symposium on Quality Electronic Design

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All synchronous CMOS integrated systems have to pay some sequencing overhead. This overhead includes the skew and the jitter of the clock. It also includes the setup time and the clock-to-output delay of the flip-flops. This paper discusses how much energy should be allocated for sequencing in these systems. It is pointed out that providing too little energy is just as bad as providing too much. It is also argued that directly trying to minimize the energy-delay product of the sequencing subsystem is practically not the right thing to do. A model for the relationship between supply voltage, clock frequency, and power dissipation is developed and empirically verified for a SPARC V9 microprocessor. An expression for the optimal energy allocation in a system is derived. Then, based on this optimum, a methodology to design energy-efficient systems is proposed.

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A 450-MHz RISC microprocessor with enhanced instruction set and copper interconnect

Cited by 17 publications

References 6 publications

Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

Design and Implementation of a Simple Cache Simulator in Java to Investigate MESI and MOESI Coherency Protocols

Compact models for estimating microprocessor frequency and power

Optimal sequencing energy allocation for CMOS integrated systems

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