A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators

Dai, Gaole; Chen, Chixiao; Ma, Shunli; Ye, Fan; Ren, Junyan

doi:10.1109/iscas.2014.6865647

Cited by 2 publications

(1 citation statement)

References 5 publications

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“…Another approach was introduced to increase the sampling rate using single-stage ADCs; multiple bits were resolved per cycle rather than 1 bit at a time. In the meantime, multi-bitsper-cycle SAR ADCs have been an area of interest to researchers [6], [10][11][12][13]. Multi-bit-per-cycle SAR ADCs can achieve higher frequencies with less power, area, and circuit complexity compared with interleaving SAR ADCs with the only disadvantage of high power consumption due to the additional comparators.…”

Section: Introductionmentioning

confidence: 99%

A 1GS/s, 9-bits DAC Interleaved (2+1)-bit Then 2-bit per Cycle SAR ADC

El-Sawy¹,

Tekin²

2020

Electrica

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This study presents a high-speed successive-approximation-register analog-to-digital converter (SAR ADC) for low-noise low-power satellite transceiver applications. The proposed system is a (2+1)-bit then 2-bit per cycle SAR ADC with a sampling rate of 1 GS/s, 9-bits resolution designed in a 65-nm standard CMOS process. This system resolves nine bits using a special switching scheme in a total of four cycles per sample. This is achieved by interleaving four capacitive digital to analog converter (C-DACs) with 1-fF unit capacitance. As the interleaving is limited only to the DACs that match well, the design is not affected by the drawbacks of full interleaving. Hence, better power efficiency and performance metrics were obtained in comparison to regular interleaved ADCs. A special timing with an additional first bit comparator is optimized to have appropriate timing margins for every step from a single 4-GHz low-noise clock source that is readily available in the 8-GHz direct conversion frontend. This comparator is reused as the active comparator in both the interleaving phases. The proposed design achieved an effective number of bits value of 8.2 bits at Nyquist rate with a power consumption of 12 mW, resulting in a figure of merit of 38.37 fJ/conversion-step.

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Section: Introductionmentioning

confidence: 99%

A 1GS/s, 9-bits DAC Interleaved (2+1)-bit Then 2-bit per Cycle SAR ADC

El-Sawy¹,

Tekin²

2020

Electrica

View full text Add to dashboard Cite

show abstract

Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits

Sree

Raj

Srinivas

2021

J. Phys.: Conf. Ser.

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Comparators play an important role in designing of SAR ADC. In this paper we achieve the required performance of SAR ADC at minimum power usage. Using of comparators will reduce the power and noise, Dynamic latch circuit used in comparator increases the speed. The differential amplifier is also discussed. Here we will get to know about Ramp ADC and also about various DAC’s like M-DAC and AUX-DAC. The time-interleaving technique is the design technique that is used to increase the speed.

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A 400-MS/s 8-b 2-b/cycle SAR ADC with shared interpolator and alternative comparators

Cited by 2 publications

References 5 publications

A 1GS/s, 9-bits DAC Interleaved (2+1)-bit Then 2-bit per Cycle SAR ADC

A 1GS/s, 9-bits DAC Interleaved (2+1)-bit Then 2-bit per Cycle SAR ADC

Study on Power Minimization techniques in SAR ADC Devices by Using Comparators Circuits

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