This paper discusses the design of chip-less RFID tags of a standard pocket size of 69 mm by 156 mm. These tags are based on lumped elements of copper metal traces constructed on a thin polyamide flexible substrate. Moreover, a low-cost single-chip Bluetooth detector circuit system is demonstrated. Two different detection methods: variable coil load coupling and optical light intensity detection were combined to yield 256 unique ID codes. In the first method, by utilizing simple 4 MHz digital drivers and an integrated analog to digital converter (ADC) in the reader controller; various inductively coupled resonant loads corresponding to multiple distinct tags could be differentiated, yielding eight different (3-bit) ID codes. The additional via-based hole pattern reflectometer method creates additional 32 distinct levels (5-bit) utilizing 650 nm visible light-emitting diode and a simple trans-impedance operational along with the same analog ADC pins of a Bluetooth controller. The printed circuit board trace coil on the two-layer low-cost FR-4 waterproof sealed detector unit is simultaneously used as a Qi wireless power receiver to charge the120 mAh 2450 Lithium Polymer (LiR) battery. The device could remain operational for more than a month with a single charge; remaining connected with a mobile device and enabling 10 readouts daily.
This study presents a high-speed successive-approximation-register analog-to-digital converter (SAR ADC) for low-noise low-power satellite transceiver applications. The proposed system is a (2+1)-bit then 2-bit per cycle SAR ADC with a sampling rate of 1 GS/s, 9-bits resolution designed in a 65-nm standard CMOS process. This system resolves nine bits using a special switching scheme in a total of four cycles per sample. This is achieved by interleaving four capacitive digital to analog converter (C-DACs) with 1-fF unit capacitance. As the interleaving is limited only to the DACs that match well, the design is not affected by the drawbacks of full interleaving. Hence, better power efficiency and performance metrics were obtained in comparison to regular interleaved ADCs. A special timing with an additional first bit comparator is optimized to have appropriate timing margins for every step from a single 4-GHz low-noise clock source that is readily available in the 8-GHz direct conversion frontend. This comparator is reused as the active comparator in both the interleaving phases. The proposed design achieved an effective number of bits value of 8.2 bits at Nyquist rate with a power consumption of 12 mW, resulting in a figure of merit of 38.37 fJ/conversion-step.
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