A 1GS/s, 9-bits DAC Interleaved (2+1)-bit Then 2-bit per Cycle SAR ADC

Abstract

This study presents a high-speed successive-approximation-register analog-to-digital converter (SAR ADC) for low-noise low-power satellite transceiver applications. The proposed system is a (2+1)-bit then 2-bit per cycle SAR ADC with a sampling rate of 1 GS/s, 9-bits resolution designed in a 65-nm standard CMOS process. This system resolves nine bits using a special switching scheme in a total of four cycles per sample. This is achieved by interleaving four capacitive digital to analog converter (C-DACs) with 1-fF unit capacitance. As the interleaving is limited only to the DACs that match well, the design is not affected by the drawbacks of full interleaving. Hence, better power efficiency and performance metrics were obtained in comparison to regular interleaved ADCs. A special timing with an additional first bit comparator is optimized to have appropriate timing margins for every step from a single 4-GHz low-noise clock source that is readily available in the 8-GHz direct conversion frontend. This comparator is reused as the active comparator in both the interleaving phases. The proposed design achieved an effective number of bits value of 8.2 bits at Nyquist rate with a power consumption of 12 mW, resulting in a figure of merit of 38.37 fJ/conversion-step.