A 4 kbit synchronous static random access memory based upon delta-doped complementary heterostructure insulated gate field effect transistor technology

Grider, David; Mactaggart, I.R.; Nohava, J.C.; Stronczer, J.; Ruden, P.P.; Nohava, Thomas; Fulkerson, D.E.; Tetzlaff, D.

doi:10.1109/gaas.1991.172636

Cited by 23 publications

(2 citation statements)

References 4 publications

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“…'Fast' refers to memories explicitly designed for high speed, 'low-V' refers to memories designed at a voltage significantly lower than the norm in that category and at that gate length, comp refers to complementary. [127,128].…”

Section: Modementioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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This paper describes the use of low-current-density tunnelling devices to obtain dense low-power (sub-100 nW/bit) compound semiconductor static random access memory (SRAM); this cell power is over two orders of magnitude lower than the best previously demonstrated in III-V materials. This same circuit topology promises orders of magnitude reduction in static power dissipation for silicon memories, assuming a suitable Si-based negative differential resistance device, at sub-pA current levels, is developed. The concept of low-standby-power tunnelling-based SRAM (TSRAM) is presented in the context of a scaling theory for all memories and a comparison is given across technologies. Experimental results for a 50 nW TSRAM gain cell using ultralow current density (~1 A cm-2) resonant tunnelling diodes and low-leakage heterostructure field-effect transistors are discussed. We describe a one-transistor TSRAM cell, verify its operation, and discuss merits of TSRAM relative to other memory types. Silicon TSRAM standby power is projected to be lower than that of conventional-style silicon SRAM or DRAM.

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Section: Modementioning

confidence: 99%

Tunnelling-based SRAM

Wagt

1999

Nanotechnology

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“…Previous studies of 1 pm gate length C-HIGFET devices and circuits have explored the dependence of the performance of these devices and circuits on the doping profile beneath the InGaAs channel and on the composition of the AIGaAs gate barrier (1)(2)(3)(4)(5). It hais been shown that a planar ndoped layer in the GaAs buffer region below the lnyGal-yAs channel can adjust the threshold voltages of n-and p-channel devices anld that it tends to reduce subthreshold leakage and output conductance of the p-channel device thus giving it much improved operating characteristics.…”

Section: Introductionmentioning

confidence: 99%

0.7 micron gate length complementary Al/sub 0.75/Ga/sub 0.25/As/In/sub 0.25/Ga/sub 0.75/As/GaAs HIGFET technology for high speed/low power digital circuits

Grider

Ruden²,

Nohava

et al. 1992

International Technical Digest on Electron Devices Meeting

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Alo.75Gao,25As/lno,2~Ga0.75As/G8As HIGFE P Technology for High Abstract Results are presented from the first submicron gate length Complementary Hetwostructure Insulated Gate Field Effect Transistor (C-HIGFET) devices and circuitls (n-and p-HIGFET gate lengths of 0.7 pm). Thils reduction in gate length results in a factor of two increase in the switching speed of C-HIGFET gates, and a 35% reduction in switchingpowerhquency without any corresponding increase in the standby power consumption. Fully functional 4Kbit SRAMs have been fabricated using this submicron C-HIGFET technology, and operation of 4Kbit SRAMs at clock frequencies of up to 360 MHz have been demonstrated. 12.6.4 334-1EDM 92

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Compound Semiconductor Device Processing

Parsey

2013

Materials Science and Technology

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The sections in this article are Introduction Doping Processes Ion Implantation Diffusion Methods Epitaxial Methods Isolation Methods Mesa Etching Ion Implantation Isolation Sidegating and Backgating Diffusion Etching Techniques Wet Etching Dry Etching Ohmic Contacts Schottky Barriers and Gates Annealing Dielectrics and Interlayer Isolation Resistors Metallization and Liftoff Processes Metallization Liftoff Processes Backside Processing and Die Separation Backside Processing Die Separation

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A 4 kbit synchronous static random access memory based upon delta-doped complementary heterostructure insulated gate field effect transistor technology

Cited by 23 publications

References 4 publications

Tunnelling-based SRAM

Tunnelling-based SRAM

0.7 micron gate length complementary Al/sub 0.75/Ga/sub 0.25/As/In/sub 0.25/Ga/sub 0.75/As/GaAs HIGFET technology for high speed/low power digital circuits

Compound Semiconductor Device Processing

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