A 4-GS/s 8-bit two-channel time-interleaved folding and interpolating ADC

Jiang, Fan; Wu, Danyu; Zhou, Lei; Wu, Jin; Jin, Zhi; Liu, Xinyu

doi:10.1007/s11432-013-5019-y

Cited by 1 publication

(2 citation statements)

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“…There are CMOS design examples, in which these switching pulses are generated such as in [4] to achieve a design with higher sampling rate, low noise, and high reliability. SiGe or InP based fabrication technologies are also preferred for that purpose [14][15][16]. Moreover, using different ADC architectures for each channel may be another possible solution.…”

Section: Introductionmentioning

confidence: 99%

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A 10 GS/s time-interleaved ADC in 0.25 micrometer CMOS technology

Aytar

Tangel

Afacan

2017

Journal of Electrical Engineering

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This paper presents design and simulation of a 4-bit 10 GS/s time interleaved ADC in 0.25 micrometer CMOS technology. The designed TI-ADC has 4 channels including 4-bit flash ADC in each channel, in which area and power efficiency are targeted. Therefore, basic standard cell logic gates are preferred. Meanwhile, the aspect ratios in the gate designs are kept as small as possible considering the speed performance. In the literature, design details of the timing control circuits have not been provided, whereas the proposed timing control process is comprehensively explained and design details of the proposed timing control process are clearly presented in this study. The proposed circuits producing consecutive pulses for timing control of the input S/H switches (ie the analog demultiplexer front-end circuitry) and the very fast digital multiplexer unit at the output are the main contributions of this study. The simulation results include +0.26/−0.22 LSB of DNL and +0.01/−0.44 LSB of INL, layout area of 0.27 mm2, and power consumption of 270 mW. The provided power consumption, DNL and INL measures are observed at 100 MHz input with 10 GS/s sampling rate.

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Section: Introductionmentioning

confidence: 99%

“…Moreover, using different ADC architectures for each channel may be another possible solution. In addition, successive approximation register (SAR) [17][18][19] and pipeline or folding [16,20,21] type of ADC structures may also be used in order to increase the resolution and reduce the layout area and power consumption further.…”

Section: Introductionmentioning

confidence: 99%