A 4.6GHz MDLL with &amp;#x2212;46dBc reference spur and aperture position tuning

Ali, Tamer; Hafez, Amr Amin; Drost, Robert; Ho, Ron; Yang, Chih-Kong Ken

doi:10.1109/isscc.2011.5746400

Cited by 19 publications

(24 citation statements)

References 6 publications

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“…7(a) and (b), respectively, and compare them with those corresponding values attained from MC of our analytical model (15). As can be observed, for small delay SDs, the derived expressions match the simulations.…”

Section: And E[ansupporting

confidence: 65%

“…As indicated previously by (15), the synthesizer SCR is the ratio distribution of Rayleigh random variable Sn over the random variable C, i.e. the magnitude of the fundamental tone.…”

Section: B Magnitude Of Spur-to-carrier Ratio (Scr)mentioning

confidence: 98%

“…4 compares the MC histogram of the SCR distribution obtained from our reference behavioral model, with that of attained from the analytical model (15). Note that for the simulations presented in the current section as well as in Section IV, we utilize the following parameters, unless otherwise specified.…”

Section: Analytical Modeling Using Fourier Seriesmentioning

confidence: 99%

“…Fig. 9 plots the calculated mean SCR values from the closed-form expression (33) and compares them with the MC-simulated SCR of the analytical model (15). Shown in Fig.…”

Section: Closed-form Expression Accuracymentioning

confidence: 99%

“…Fig. 9(c) demonstrates that a less than 1 dB error in SCR estimation can be obtained even for a small delay SD of σ/µ = 0.2%, and with reasonable DCD and SPE values of Tdcd = 10 ps and Tspe = 2 ps, achievable in state-of-the-art CMOS implementations [2], [6], [15].…”

Section: Closed-form Expression Accuracymentioning

confidence: 99%

See 4 more Smart Citations

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Ojani

Mesgarzadeh

Alvandpour

2014

IEEE Trans. Circuits Syst. I

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Abstract-Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the outof-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of -45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.Index Terms-delay mismatch, DLL, duty cycle distortion, edge-combiner, frequency synthesizer, harmonic spur, periodic jitter, static phase error.

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Section: And E[ansupporting

confidence: 65%

“…As indicated previously by (15), the synthesizer SCR is the ratio distribution of Rayleigh random variable Sn over the random variable C, i.e. the magnitude of the fundamental tone.…”

Section: B Magnitude Of Spur-to-carrier Ratio (Scr)mentioning

confidence: 98%

Section: Analytical Modeling Using Fourier Seriesmentioning

confidence: 99%

“…Fig. 9 plots the calculated mean SCR values from the closed-form expression (33) and compares them with the MC-simulated SCR of the analytical model (15). Shown in Fig.…”

Section: Closed-form Expression Accuracymentioning

confidence: 99%

Section: Closed-form Expression Accuracymentioning

confidence: 99%

See 3 more Smart Citations

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Ojani

Mesgarzadeh

Alvandpour

2014

IEEE Trans. Circuits Syst. I

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A reduced reference spur multiplying delay‐locked loop

Wang

Kwaśniewski

2015

Circuit Theory & Apps

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This letter presents a reduced reference spur multiplying delay-locked loop (MDLL). The static phase offset (SPO) between the reference edge and its counterpart of MDLL output is the dominant mechanism causing reference spur in the spectrum of MDLL output. SPO is mainly caused by the non-idealities on charge pump (e.g., sink and source current mismatch) and control line (e.g., gate leakage of loop filter and voltagecontrolled delay line control circuit). With a high-gain stage inserting between phase detector/phase frequency detector and charge pump, the equivalent SPO has been decreased by a factor equal to the gain of the gain stage. To validate the effectiveness of the proposed technique, an MDLL is implemented in TSMC CMOS 0.18 μm process. The simulation result shows that À60.1 dBc reference spur was achieved at center frequency of 1.8 GHz.

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Robust high‐multiplication factor MDLL using IIR filter‐based accumulated jitter reduction

Jee

2018

Electron. lett.

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A high-multiplication factor multiplying delay-locked loop (MDLL) with infinite impulse response filter-based accumulated jitter reduction technique is presented. In every output clock cycle, the proposed jitter reduction loop samples the periodic jitter, accumulates it, and subtracts accumulated jitter from the next output clock period. The proposed technique is applied to 10 MHz MDLL with 32 kHz reference clock, a multiplication factor of 313, shows 38% jitter reduction, and greatly improves MDLL locking even with high-supply noise. The MDLL implemented in 0.18 μm CMOS process consumes 42 μW and the core area is 0.043 mm 2 .

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A 4.6GHz MDLL with −46dBc reference spur and aperture position tuning

Cited by 19 publications

References 6 publications

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

A reduced reference spur multiplying delay‐locked loop

Robust high‐multiplication factor MDLL using IIR filter‐based accumulated jitter reduction

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