A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

Leibowitz, Brian; Palmer, R.; Poulton, John W.; Frans, Yohan; Li, S.; Wilson, John; Bucher, Michael; Fuller, Andrew M.; Eyles, John; Aleksic, Milivoje; Greer, Thomas H.; Nguyễn, Nam Thành

doi:10.1109/jssc.2010.2040230

Cited by 61 publications

(28 citation statements)

References 10 publications

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“…The high-speed reference clocks distributed across both the controller and DRAM interfaces. Based on the command traffic from the memory host controller, the appropriate low power states are employed (Leibowitz et al, 2010;Balamurugan et al, 2008;Lee et al, 2009;Poulton et al, 2007).…”

Section: Discussionmentioning

confidence: 99%

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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Problem statement:In any multimedia processor, controller may consume most of the onchip memory resources. The memory requirement is directly depends on algorithm shared by different blocks, so leads to failure in the system models. Approach: This study presents the implementation of DLL unit used for memory optimization. Various aspects of the underlying coarse lock detector are explored and modifications are made with software reference implementation. The whole system is implemented in 0.18 µm CMOS technology, where an input reference clock to an outgoing data clock monitors and true locking is initialized with 50% duty cycle correction. Results: From the measurement result of DLL operation, the output clock jitter is analyzed. Power consumption of DLL including large size output buffer is about few mW. Conclusion: The great challenge in this implementation is communication bandwidth, has brought to process variation and power state reduction techniques. In addition, inefficiency of computing capacity and simultaneous switching noise is reduced in the real time applications.

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Section: Discussionmentioning

confidence: 99%

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

O.¹

2012

Journal of Computer Science

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“…The consumer electronics products currently on the market demand higher speed data communication as the amount of digital data required increases year by year [1]. In particular, as the generation transitions from 4K2K to 8K4K, the amount of display data has become four times as great.…”

Section: Introductionmentioning

confidence: 99%

An ultra-wide range (0.01–240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator

Ebuchi

Toshikawa

Watanabe

et al. 2018

IEICE Electron. Express

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This paper proposes an ultra-wide range transmitter with a latched AC-coupled driver (LACD) and a dummy data transient generator (DDTG). The LACD expands the low-frequency range by preventing the capacitor discharge issue of the high-speed AC-coupled driver and the DDTG enhances the high-frequency range by generating a dummy transient pattern to stabilize the power node fluctuation induced by the dense and sparse pattern dependency in the case of coding-less application. A 24-channel test chip designed with 40-nm CMOS technology achieved an ultrawide frequency range (0.01-10 Gbps/channel) and ultra-wide bandwidth from 0.01 Gbps (0.01 Gbps × 1 channel) to 240 Gbps (10 Gbs × 24 channels) and a high area efficiency (0.0027 mm 2 /Gbps/channel). At the data rates of 5 and 10 Gbps, the jitters with DDTG were 50% lower than attained without DDTG.

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“…Recent consumer electronics products require higher speed data communication as an amount of necessary digital data is increasing year by year [1]. For example, display data is becoming to 4 times at a transition of generation from Full HD to 2K4K.…”

Section: Introductionmentioning

confidence: 99%

A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs

Ebuchi

Toshikawa

Watanabe

et al. 2014

IEICE Electron. Express

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This paper proposes a jitter suppression technique for a highspeed interface macro by decreasing the disturbance onto a power node of the macro. The power node fluctuates in accordance with the output data pattern from the macro. Namely, it becomes lower at the dense data pattern and returns near to an initial value at the sparse data pattern. This fluctuation causes the jitter and deteriorates the data eye on the output node. The proposed scheme relaxes the dense and sparse pattern dependency by decreasing the fluctuation. Simulation results show a significant suppression of i) the power node fluctuation from 20 mV to 8 mV, and ii) the jitter from 160 ps to 60 ps on the data eye. Clear data eye openings were obtained at various data rates on actual measurements.

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A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

Cited by 61 publications

References 10 publications

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

High Performance Computing on Fast Lock Delay Locked Loop with Low Power State and Simultanoeus Switching Noise Reduction

An ultra-wide range (0.01–240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator

A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs

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