A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing

Chang, Meng‐Fan; Lin, Chien-Chen; Lee, Albert; Chiang, Yen-Ning; Kuo, C. P.; Yang, Geng-Hau; Tsai, Hung-Pei; Chen, Tien-Fu; Sheu, Shyh-Shyuan

doi:10.1109/jssc.2017.2681458

Cited by 60 publications

(31 citation statements)

References 11 publications

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“…Ly et al [7] extensively characterize a ReRAM-based 2T2R TCAM circuit. Chang et al [8] propose a 3T1R TCAM based on multilevel ReRAM cell to achieve high density. Regarding IM-DP, Chen et al [12] use two 1T1R ReRAM bit-cells to store ternary weights (+1, −1, 0) of neural networks and implements MAC based on current accumulation.…”

Section: B Related Workmentioning

confidence: 99%

“…Computing in-memory (CIM) [4]- [13] is an attractive solution to reduce the energy and latency cost of memory access by performing specific computations directly inside the memory macro without reading out operands and sending to ALUs. For example, ternary content addressable memory (TCAM) [4]- [8] is a critical component to achieve fast searches. Rather than reading out data row-by-row and sending to ALUs for comparison, TCAM performs bit-wise XOR/XNOR between the search key and all stored data to get the match result in one cycle.…”

Section: Introductionmentioning

confidence: 99%

“…However, many prior CIM works [5]- [12] only focus on one specific CIM function. Moreover, most ReRAM-based TCAM [6]- [8] cannot support row-wise memory access due to the conflicts between shared horizontal match-lines in TCAM and shared vertical bit-lines in conventional memory architectures. Although conventional 6T SRAM can support TCAM operations by adding additional access transistors, the large cell area overhead (e.g., two 10T cells to store 1b TCAM data in [5]) brings a great challenge to highcapacity TCAM systems.…”

Section: Introductionmentioning

confidence: 99%

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A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Chen

Kim

et al. 2021

IEEE Open J. Circuits Syst.

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Resistive random access memory (ReRAM)-based computing in-memory (CIM) is a promising solution to overcome the von-Neumann bottleneck in conventional computing architectures. We propose a reconfigurable ReRAM architecture using a novel 4T2R bit-cell that supports non-volatile storage and two types of CIM operations: i) ternary content addressable memory (TCAM) and ii) in-memory dot product (IM-DP) for neural networks. The proposed 4T2R cell occupies a smaller area than prior SRAMbased CIM bit-cells. A 128 × 128 ReRAM macro is designed in 40nm CMOS technology. For TCAM operations, it allows a search word-length of 128 bits. For IM-DP operations, it can compute parallel dot products using binary inputs and ternary weights. The simulated search delay for TCAM operation is 0.92 ns at VDD = 0.9 V and the simulated energy efficiency for IM-DP operation is 223.6 TOPS/W at VDD = 0.7 V. Monte-Carlo simulations show a standard deviation of 4.9% in accumulate operation for IM-DP which corresponds to a classification accuracy of 95.7% on the MNIST dataset and 81.7% on the CIFAR-10 dataset. INDEX TERMS Resistive random access memory (ReRAM), ternary content addressable memory (TCAM), computing in-memory (CIM), reconfigurable architecture.

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Section: B Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Chen

Kim

et al. 2021

IEEE Open J. Circuits Syst.

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“…TCAM finds its applications as look-up table in networking routers [1,2], as translations-look-aside buffers (TLBs) caches in microprocessors [3,4], as database accelerators in big-data analytics [4,5], as a filter when storing signature patterns in Internet-of-Things [6,7], as Local binary patterns recognition system in image processing and DNA sequence matching [8,9]. However, the dedicated bit comparison circuitry in each native TCAM cell lowers its memory density and the inherent massive parallelism makes native TCAM power hungry and expensive [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

Ullah

Lee

2018

Electronics

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Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

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“…This limits storage capacity of TCAM circuits to tens of Mbs [2][3] in standard memory structures, and takes up valuable silicon real-estate in neuromorphic computing spiking neural network chips [4][5]. In order to increase storage density, RRAM-based TCAM cells have been proposed [6][7][8][9][10]. However, one drawback of RRAM-based with respect to SRAM-based TCAMs is the relatively small ON/OFF current ratio of the memory elements (~ for MOSFET compared to 10-100 for RRAMs).…”

Section: Introductionmentioning

confidence: 99%

In-depth Characterization of Resistive Memory-Based Ternary Content Addressable Memories

Giraud

Noël

et al. 2018

2018 IEEE International Electron Devices Meeting (IEDM)

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Resistive Memory (RRAM)-based Ternary Content Addressable Memories (TCAMs) were developed to reduce cell area, search energy and standby power consumption beyond what can be achieved by SRAM-based TCAMs. In previous works, RRAM-based TCAMs have already been fabricated, but the impact of RRAM reliability on TCAM performance has never been proven until now. In this work, we fabricated and extensively tested a RRAMbased TCAM circuit. We show that a trade-off exists between search latency and reliability in terms of match/mismatch detection and search/read endurance, and that a RRAM-based TCAM is an ideal building block in multi-core neuromorphic architectures. These ones would not be affected by long latency time and limited write endurance, and could greatly benefit from their high-density and zero standby power consumption.

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A 3T1R Nonvolatile TCAM Using MLC ReRAM for Frequent-Off Instant-On Filters in IoT and Big-Data Processing

Cited by 60 publications

References 11 publications

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

In-depth Characterization of Resistive Memory-Based Ternary Content Addressable Memories

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