In-depth Characterization of Resistive Memory-Based Ternary Content Addressable Memories

Abstract

Resistive Memory (RRAM)-based Ternary Content Addressable Memories (TCAMs) were developed to reduce cell area, search energy and standby power consumption beyond what can be achieved by SRAM-based TCAMs. In previous works, RRAM-based TCAMs have already been fabricated, but the impact of RRAM reliability on TCAM performance has never been proven until now. In this work, we fabricated and extensively tested a RRAMbased TCAM circuit. We show that a trade-off exists between search latency and reliability in terms of match/mismatch detection and search/read endurance, and that a RRAM-based TCAM is an ideal building block in multi-core neuromorphic architectures. These ones would not be affected by long latency time and limited write endurance, and could greatly benefit from their high-density and zero standby power consumption.

Variability analysis of resistive ternary content addressable memories

“…As a TCAM design example, we considered using a commercial RRAM device that is available for fabrication by Circuits Multi‐Projects in 1T1R structure. This device has 3.1 and 570 k Ω average resistance values, with and 30% tolerance 59 . Figure 14 depicts the probability of error and search delay with this device versus changing the row width.…”

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

“…Huang et al [6] propose a 4T2R TCAM cell based on RC-filters to reduce the ReRAM stress during search operations. Ly et al [7] extensively characterize a ReRAM-based 2T2R TCAM circuit. Chang et al [8] propose a 3T1R TCAM based on multilevel ReRAM cell to achieve high density.…”

“…3 shows the layout and schematic of the proposed 4T2R bit-cell. In the schematic, two transistors (N1 and N2) and two ReRAM devices (Q and QB) form a differential 2T2R bit-cell which has been employed in CIM by several prior works [7], [14]. The differential 2T2R bit-cell has two bit-lines (BL and BLB) shared by each column while the source-line (SL) and the word-line (WL) are shared by each row.…”

“…Since the 4T2R bit-cell is built on top of the differential 2T2R bit-cell [7], [14] which is formed by two 1T1R bitcells that share a common SL, the biasing conditions for read and write operations in NVM mode are similar to that of the 1T1R bit-cell. N3 and N4 are not used in NVM mode so they can be turned off by grounding MLL/MLR and CSL.…”

“…To tackle these challenges, we propose a reconfigurable R-CIM macro using a novel 4T2R bit-cell. The key idea is to add two access transistors to a differential 2T2R ReRAM bit-cell that has been well studied [7], [14]. The proposed R-CIM structure can function as a non-volatile storage system as well as accelerators for TCAM and IM-DP operations.…”