A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Chen, Yuzong; Lu, Lu; Kim, Bongjin; Kim, Tony Tae-Hyoung

doi:10.1109/ojcas.2020.3042550

Cited by 19 publications

(8 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…VR-XNOR [46] proposes a memristor-based Voltage-Resistance XNOR (VR-XNOR) cell with a filter bank for binary convolution acceleration. Some papers also use traditional memories, especially SRAM, as processing elements [44] SRAM-CIM [36] XNOR-BNN [40] XNOR-BNN [40] 2T2R-TCAM [45] VR-XNOR [46] TNN Ternary Mul., or Gated-XNOR + Popcnt 4T2R-IM-DP [47] TiM-DNN [24] SpinLiM [48] XNOR-SRAM [25] TeC-Cell [49] IMC-CD-TNN [50] Ter-LiM [51] BWN Dense Addition ParaPIM [29] MRIMA [30] TWN Sparse Addition This Work…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

“…Thus most TNN accelerators build dedicated processing units for 2-bit ternary multiplications. 4T2R-IM-DP [47] provides a ReRAM-based IMC 4T2R bit-cell to enable In-Memory Dot Product (IM-DP) for TNNs. Ter-LiM [51] implements a Ternary Logic-in-Memory (Ter-LiM) scheme based on the memristive dual-crossbar structure with multilevel memristor cells.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

See 1 more Smart Citation

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

Convolutional Neural Networks (CNNs) demonstrate excellent performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity than BWNs, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of activations and weights and increase the parallelism across memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with a State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% average sparsity.

show abstract

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

Zhu

Duong

Chen

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…3) ReRAM PIM for Versatile Functions: Even though MAC is one of the most common tasks accelerated by PIM, modern data-intensive applications require many other functions such as Boolean logic and search operations. Various ReRAM-based cell structures such as 4T2R and 2T2R are reported to support versatile PIM operations on the same array [49], [50]. Fig.…”

Section: F New Directions For Reram Pim Research 1) Rerammentioning

confidence: 99%

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

Kim

Xie

Chen

et al. 2022

IEEE J. Emerg. Sel. Topics Circuits Syst.

Self Cite

View full text Add to dashboard Cite

Artificial intelligence (AI) and machine learning (ML) are revolutionizing many fields of study, such as visual recognition, natural language processing, autonomous vehicles, and prediction. Traditional von-Neumann computing architecture with separated processing elements and memory devices have been improving their computing performances rapidly with the scaling of process technology. However, in the era of AI and ML, data transfer between memory devices and processing elements becomes the bottleneck of the system. To address this data movement issue, memory-centric computing takes an approach of merging the memory devices with processing elements so that computations can be done in the same location without moving any data. Processing-In-Memory (PIM) has attracted research community's attention because it can improve the energy efficiency of memory-centric computing systems substantially by minimizing the data movement. Even though the benefits of PIM are well accepted, its limitations and challenges have not been investigated thoroughly. This paper presents a comprehensive investigation of state-of-the-art PIM research works based on various memory device types, such as static-random-access-memory (SRAM), dynamic-random-access-memory (DRAM), and resistive memory (ReRAM). We will present the overview of PIM designs in each memory type, covering from bit cells, circuits, and architecture. Then, a new software stack standard and its challenges for incorporating PIM with the conventional computing architecture will be discussed. Finally, we will discuss various future research directions in PIM for further reducing the data conversion overhead, improving test accuracy, and minimizing intra-memory data movement.

show abstract

“…SRAM-CIM [39] raises an SRAM Computing-In-Memory (SRAM-CIM) unit-macro for binarized fully connected neural networks. XNOR-SRAM [28] presents an [45] SRAM-CIM [39] XNOR-BNN [43] XNOR-BNN [43] 2T2R-TCAM [46] VR-XNOR [47] TNN Ternary Mul., or Gated-XNOR + Popcnt 4T2R-IM-DP [48] TiM-DNN [27] SpinLiM [49] XNOR-SRAM [28] TeC-Cell [50] IMC-CD-TNN [51] Ter-LiM [52] BWN Dense Addition ParaPIM [32] MRIMA [33] TWN Sparse Addition This Work SRAM macro that supports ternary-XNOR-and-accumulate operations for both BNNs and TNNs. TNN acceleration is another active research area besides BNN acceleration.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

“…The dominant operation in TNNs is ternary multiplication which is equivalent to a Gated-XNOR followed by a popcnt, so most TNN accelerators build dedicated processing units for 2-bit ternary multiplications. 4T2R-IM-DP [48] provides a ReRAM-based IMC 4T2R bit-cell which enables In-Memory Dot Product (IM-DP) for TNNs. Ter-LiM [52] implements a Ternary Logic-in-Memory (Ter-LiM) scheme based on the memristive dual-crossbar structure with multi-level memristor cells.…”

Section: B In-memory-computing Accelerators For Quantized Cnnsmentioning

confidence: 99%

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Zhu,

Duong,

Chen

et al. 2022

Preprint

View full text Add to dashboard Cite

Convolutional Neural Networks (CNNs) demonstrate great performance in various applications but have high computational complexity. Quantization is applied to reduce the latency and storage cost of CNNs. Among the quantization methods, Binary and Ternary Weight Networks (BWNs and TWNs) have a unique advantage over 8-bit and 4-bit quantization. They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied. However, though TWNs have higher accuracy and better sparsity, IMC acceleration for TWNs has limited research. TWNs on existing IMC devices are inefficient because the sparsity is not well utilized, and the addition operation is not efficient.In this paper, we propose FAT as a novel IMC accelerator for TWNs. First, we propose a Sparse Addition Control Unit, which utilizes the sparsity of TWNs to skip the null operations on zero weights. Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to the memory cells. Third, we further propose a Combined-Stationary data mapping to reduce the data movement of both activations and weights and increase the parallelism of memory columns. Simulation results show that for addition operations at the Sense Amplifier level, FAT achieves 2.00× speedup, 1.22× power efficiency and 1.22× area efficiency compared with State-Of-The-Art IMC accelerator ParaPIM. FAT achieves 10.02× speedup and 12.19× energy efficiency compared with ParaPIM on networks with 80% sparsity.

show abstract

A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications

Cited by 19 publications

References 26 publications

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks

An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks

Contact Info

Product

Resources

About