A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

Arsovski, Igor; Hebig, Travis; Dobson, Daniel; Wistort, Reid

doi:10.1109/jssc.2013.2239092

Cited by 50 publications

(12 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It is worth noting that electronic RAMs have achieved a maximum speed of up to 5.3 GHz, when built on 65 nm CMOS and optimized for high performance [43], showing a trend towards slowing down and giving up their fast access time at speed of 1 GHz or even below, to benefit from lower energy consumption in the order of a few fJ/bit or less [47]. A similar trend is also observed for electronic CAMs, where performance is typically limited in the order of 500 MHz [51] and reaches the 1 GHz operation only by using pattern dependent predict-and-correct schemes, while also occupying energy consumptions in the order of 1 fJ bit −1 [50,52].…”

Section: Discussion and Future Challengessupporting

confidence: 56%

“…However, as in all these optical RAM cell demonstrations, the optical AGs have been mainly implemented as simple, unoptimized wavelength converters (WCs) [25][26][27][28][29][30][31], not tailored specifically for RAM operation, leaving room for further improvements in terms of high-speed operation. As a result, optical RAM cell demonstrations have so far exhibited speed capabilities only up to 5 Gb s −1 [25,27] not managing to outperform the performance of state-of-the-art electronics RAMs [43][44][45][46][47][48][49][50][51][52][53]. Still, in order to efficiently minimize the disparity between slow AL and continuously increasing optical transmission line rates, the development of optical CAMs is also required in order to synergize with fast optical RAM circuits towards enabling light-based AL tables with high-speed capabilities of 10 Gb s −1 and beyond.In this communication we present our vision and the latest progress on both functional elements, i.e.…”

mentioning

confidence: 99%

See 1 more Smart Citation

Optical memory architectures for fast routing address look-up (AL) table operation

et al. 2019

View full text Add to dashboard Cite

Today, the increasing demand for fast routing processes has turned the address look-up (AL) operation into one of the main critical performance operations in modern optical networks, since it conventionally relies on slow-performing AL tables. Specifically, AL memory tables are comprised of content addressable memories (CAMs) for storing a known route of the forwarding information base of the router, and random access memories (RAMs) for storing the respective output port for this route. They thus allow for a one-cycle search operation of a packet's destination address, yet they typically operate at speeds well below 1 GHz, in contrast with the vastly increasing optical line rates. In this paper, we present our overall vision towards light-based optical AL memory functionalities that may facilitate faster router AL operations, as the means to replace slow-performing electronic counterparts. In order to achieve this, we report on the development of a novel optical RAM cell architecture that performs for the first time with a speed of up to 10 Gb s −1 , as well as our latest works on multi-bit 10 Gb s −1 optical CAM cell architectures. Specifically, the proposed optical RAM cell exploits a semiconductor optical amplifier-Mach-Zehnder interferometer in a push-pull configuration and deep saturation regime, doubling the speed of prior optical RAM cell configurations. Errorfree write/read operation is demonstrated with a peak power penalty of 6.2 dB and 0.4 dB, respectively. Next, we present the recent progress on optical CAM cell architectures, starting with an experimental demonstration of a 2-bit optical CAM match-line architecture that achieves an exact bitwise search operation of an incoming 2-bit destination address at 10 Gb s −1 , while the analysis is also extended to a numerical evaluation of a multi-cell 4-bit CAM-based row architecture with wavelength division multiplexed outputs for fast parallel memory operations at speeds of up to 4×20 Gb s −1 . Finally, we present a comparative study between electronic and optical RAMs and CAMs in terms of energy and speed and discuss the further challenges towards our vision. entries, even causing the depletion of the remaining IPv4 address space and leading to the advent of an IPv6 protocol with a quadrupled need for address look-up (AL) requirements [5]. This increasing need for faster routing functionalities, including AL, which also requires fast hardware memories to perform fast look-up of the packet's destination address immediately upon its arrival and across the forwarding information base (FIB) of the router.On the path to speeding up hardware memory and lower latency times when fetching data, state-of-the-art highly performing electronic static random access memory (RAM) cell technology has managed to achieve operation up to 5 GHz [6][7][8]. However, RAMs are inherently limited in fast AL as, owing to the address-based fetching of data, they would require multiple sequential random access to the memory and consecutive searches of the desired content. As a re...

show abstract

Section: Discussion and Future Challengessupporting

confidence: 56%

mentioning

confidence: 99%

Optical memory architectures for fast routing address look-up (AL) table operation

et al. 2019

View full text Add to dashboard Cite

show abstract

“…This value can be reduced by orders of magnitudes when shifting to more sophisticated low-power III/V-on-SOI photonic crystal technologies with nm-scale dimensions and power consumptions of a few mW [55], towards energy efficiencies of a few fJ/bit, comparable to electronics [6,20,21]. Meanwhile the use of the envisioned high-speed multi-bit optical ML architectures technology provides a possible path towards circumventing the use of power-hungry cost expensive power conversion at SERDES equipment, that can allocate up to half of the power consumption of a low power transceiver [24].…”

Section: Future Challenges and Discussionmentioning

confidence: 99%

“…These results imply that electronic T-CAMs are hard-limited by the underlying interconnect network and can rarely reach the barrier of 1 Gb/s. This barrier was only recently broken using alternative non-optimal techniques that may use early predict/late-correct schemes [21], which are yet known to be heavily dependent on data patterns [17]. A second speed enhancement technique suggests inserting four T-CAM arrays performing in parallel at a slower rate of 4 × 400 MHz [6], necessitating even more complex Application Specific Integrated Circuit (ASIC) for deserialization and further exacerbating the energy requirements of routers, which reached their rack-power density limits in 2005 [4,22,23].…”

Section: Introductionmentioning

confidence: 99%

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

et al. 2017

View full text Add to dashboard Cite

Electronic Content Addressable Memories (CAM) implement Address Look-Up (AL) table functionalities of network routers; however, they typically operate in the MHz regime, turning AL into a critical network bottleneck. In this communication, we demonstrate the first steps towards developing optical CAM alternatives to enable a re-engineering of AL memories. Firstly, we report on the photonic integration of Semiconductor Optical Amplifier-Mach Zehnder Interferometer (SOA-MZI)-based optical Flip-Flop and Random Access Memories on a monolithic InP platform, capable of storing the binary prefix-address data-bits and the outgoing port information for next hop routing, respectively. Subsequently the first optical Binary CAM cell (B-CAM) is experimentally demonstrated, comprising an InP Flip-Flop and a SOA-MZI Exclusive OR (XOR) gate for fast search operations through an XOR-based bit comparison, yielding an error-free 10 Gb/s operation. This is later extended via physical layer simulations in an optical Ternary-CAM (T-CAM) cell and a 4-bit Matchline (ML) configuration, supporting a third state of the "logical X" value towards wildcard bits of network subnet masks. The proposed functional CAM and Random Access Memories (RAM) sub-circuits may facilitate light-based Address Look-Up tables supporting search operations at 10 Gb/s and beyond, paving the way towards minimizing the disparity with the frantic optical transmission linerates, and fast re-configurability through multiple simultaneous Wavelength Division Multiplexed (WDM) memory access requests.

show abstract

“…Some techniques reduced the SL power by recycling the charge on SLs [15], [23] or by lowering the swing voltage on SLs [3]. The pipelined hierarchical search scheme reduced the SL power by activating a few sub-SLs selected in the preceding pipeline stage [14].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme

Yang

2015

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

This paper proposes a low-power effective memorysize expanded ternary content addressable memory (TCAM). The IP address of IPv6 extends to 128 bits, where the prefix bits store '0' or '1' and the remaining bits store 'X' (don't care). Most prefixes are much shorter than 128 bits, so many TCAM cells store 'X'. The proposed data-relocation TCAM (DR-TCAM) increases the number of IP addresses stored in the TCAM by relocating the data in the prefix bits into 'X' cells. The DR-TCAM has four types of banks. The type-0 bank is empty and inactivated. The type-1 and type-2 banks store four 32 bit words and two 64 bit words instead of a 128 bit word in the type-3 bank, respectively. Therefore, the type-1 and type-2 banks store four and two times larger IP addresses, respectively. In the simulation, the area and power consumption of the DR-TCAM decreased to 34% and 36% of those of the conventional TCAM for 4 K IP addresses, respectively. The DR-TCAM chip with 256 × 128 bit TCAM cells and 8 banks was fabricated using a 1.2 V 0.13 µm CMOS process. Its area was 0.87 mm 2 . Its energy/bit/search was 1.3 fJ at 200 MHz clock frequency when 4 banks were activated to store 256 IP addresses. Index Terms-Data relocation, don't care, low power, memory expansion, ternary content addressable memory (TCAM).Byung-Do Yang received the B.S., M.S., and Ph.D. degrees in electrical engineering from Korea

show abstract

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation

Cited by 50 publications

References 9 publications

Optical memory architectures for fast routing address look-up (AL) table operation

Optical memory architectures for fast routing address look-up (AL) table operation

Integrated Optical Content Addressable Memories (CAM) and Optical Random Access Memories (RAM) for Ultra-Fast Address Look-Up Operations

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme

Contact Info

Product

Resources

About