A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI

Çelik, Firat; Akkaya, Ayça; Tajalli, Armin; Leblebici, Yusuf

doi:10.1109/tvlsi.2021.3068242

Cited by 13 publications

(3 citation statements)

References 16 publications

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“…The driver has two basic constructs, current mode logic (CML) and source-series terminated (SST). When the output swing is the same, the current required by the voltage mode driver is only 1/4 of the current mode driver [25]. The SST driver circuit has better linearity than the CML driver circuit for high-speed transmission, and the SST driver circuit can increase the height and width of the eye, so this paper used the SST driver circuit to drive the whole transmitter [5].…”

Section: Driver Circuit Designmentioning

confidence: 99%

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

Tang

Shi

et al. 2022

Electronics

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To reduce the high bit error rate of serial transceivers under strong channel attenuation, a low-power 112 Gb/s SerDes transmitter was designed using a duo-binary PAM4 modulation technology. By adopting duo-binary PAM4 modulation technology, the problem of the low bandwidth utilization of a high-speed PAM4 (pulse amplitude modulation 4) signal was improved. The problem of high jitter caused by charge sharing and the limited bandwidth of a 4:1 high-speed MUX was improved by using precharging auxiliary transistors. The system power consumption of the transmitter was reduced by using a 7-bit weighted voltage-driven digital-to-analog converter (DAC). The transmitter was designed with a 28 nm CMOS process and powered by a voltage of 0.9 V. The simulation results showed that when the channel attenuation was 20.9 dB, the transmitter could work at 112 Gb/s, the power consumption was 2.02 pJ/bit, and the linearity was 96.7%.

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Section: Driver Circuit Designmentioning

confidence: 99%

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

Tang

Shi

et al. 2022

Electronics

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“…Recent works have demonstrated that source-series terminated (SST) PAM-4 drivers exhibit good linearity due to their voltage operation mode which does not involve current mismatch [21,22,23]. Unfortunately, the output impedance matching and tunable adjustment for the feed-forward equalizer (FFE) result in heavy self-drain loads, requesting an advanced process to support a high operation speed [24,25,26]. In contrast, the current mode logic (CML) PAM-4 drivers can fully exploit the process potentials as their compact NMOS driving topology naturally features fast current switching speed and small parasitic capacitance [27].…”

Section: Introductionmentioning

confidence: 99%

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

Xu,

Zheng,

Wang

et al. 2024

IEICE Electron. Express

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This article presents a high-output-swing 64-Gb/s four-level pulse amplitude modulation (PAM-4) transmitter, in which a 4-tap hybrid feed-forward equalizer (FFE) employing both fractionally-spaced preemphasis (FS-PE) and baud-spaced de-emphasis (BS-DE) is proposed. The PE technique enlarges the output swing by directly stacking pre-distortion pulses, and naturally consumes less power as it boosts only the desired symbols. The FS-based pre/post1 taps equalize the high-frequency loss, provide a wide compensation range beyond the Nyquist frequency, and realize a flexible equalization capability, while the BS-DE-based post2 tap compensates for the low-frequency channel loss. Fabricated in a 28-nm CMOS process, the 64-Gb/s transmitter obtains a differential output swing of 1.4 V ppd with an energy efficiency of 1.53 pJ/bit.

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“…However, the channel bandwidths of such display systems are severely limited due to loss and reflections from long PCB traces and FPC (Flexible Printed Circuit) structures. Therefore, transceivers for the display interfaces should adopt advanced signaling (such as PAM-4 [4][5][6][7]) and equalization (such as FFE [8,9]) techniques to achieve such high data rates in energy-efficient ways. However, the voltage mode FFE driver suffers from high power consumption, and the PAM-4 signaling yields high sensitivity to residual ISIs.…”

mentioning

confidence: 99%

A 16.7-Gb/s full-transition avoidance PAM-4 2-tap FFE transmitter with shunt switches for display interfaces

Han

Song

Seo

et al. 2022

Preprint

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This paper describes a channel-loss-tolerant 16.7-Gb/s PAM-4 transmitter with feed-forward equalization (FFE) for display interfaces. The proposed transmitter adopts full transition avoidance (FTA) coding in combination with the 2-tap FFE to enhance the worst-case horizontal eye-opening in the presence of inter-symbol interference (ISI) and shunt switches to reduce power consumption. The transmitter test chip was fabricated in a 28-nm CMOS process and occupied 0.04 mm2. The design achieved 16.7-Gb/s (corresponding to 10 Gbaud/s) with a 0.20x wider horizontal eye-opening for a >7.2 dB loss channel while consuming 107.6mW (corresponding to 6.4 pJ/bit) from the 1.2-V supply.

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A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI

Cited by 13 publications

References 16 publications

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

A 112 Gb/s DAC-Based Duo-Binary PAM4 Transmitter in 28 nm CMOS

A high-output-swing 64-Gb/s PAM-4 transmitter with a 4-tap hybrid FFE in 28-nm CMOS

A 16.7-Gb/s full-transition avoidance PAM-4 2-tap FFE transmitter with shunt switches for display interfaces

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