A 31 ns Random Cycle VCAT-Based 4F$^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency

Song, Ki–Whan; Kim, Jin‐Young; Yoon, Jae-Man; Kim, Sua; Kim, Huijung; Chung, Hyun-Woo; Kim, Hyungi; Kim, Kanguk; Park, Hwan-Wook; Kang, Hee-Cheol; Tak, Nam-Kyun; Park, Dukha; Kim, Woo-Seop; Lee, Yeong-Taek; Oh, Youngtek; Jin, Gyoyoung; Yoo, Jung-Keun; Park, Donggun; Oh, Kyungseok; Kim, Changhyun; Jun, Young-Hyun

doi:10.1109/jssc.2010.2040229

Cited by 29 publications

(24 citation statements)

References 8 publications

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“…The only alternative for both DRAM and NAND has been the use of the third dimension by introducing vertical device architectures. For DRAM it has been realized first by stacking the capacitor on top of the access transistor, and afterwards by moving to more sophisticated vertical transistor architectures until the development of a vertical access transistor [6], which should reduce cell size to 4F 2 .…”

Section: Evolution Of Mainstream Memorymentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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a b s t r a c tMemory is a key component of any data processing system. Following the classical Turing machine approach, memories hold both the data to be processed and the rules for processing them. In the history of microelectronics, the distinction has been rather between working memory, which is exemplified by DRAM, and storage memory, exemplified by NAND. These two types of memory devices now represent 90% of all memory market and 25% of the total semiconductor market, and have been the technology drivers in the last decades. Even if radically different in characteristics, they are however based on the same storage mechanism: charge storage, and this mechanism seems to be near to reaching its physical limits. The search for new alternative memory approaches, based on more scalable mechanisms, has therefore gained new momentum. The status of incumbent memory technologies and their scaling limitations will be discussed. Emerging memory technologies will be analyzed, starting from the ones that are already present for niche applications, and which are getting new attention, thanks to recent technology breakthroughs. Maturity level, physical limitations and potential for scaling will be compared to existing memories. At the end the possible future composition of memory systems will be discussed.

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Section: Evolution Of Mainstream Memorymentioning

confidence: 99%

Emerging memories

Baldi

Bez

Sandhu

2014

Solid-State Electronics

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“…• DATE demonstrates a new core design to support emerging VCAT based cell array layout as depicted in [11]. The new core design includes sense-amplifier (SA) rotation and hybridization, conjunction restructuring, word line (WL) strapping, etc.…”

Section: Original Contributionsmentioning

confidence: 99%

“…Vertical channel access transistor (VCAT) is another transistor that has been proposed as a bitcell transistor alternative for DRAMs [11,24]. The major benefit from VCAT is area efficiency; the VCAT is a three-dimensional structure in which the channel exists vertically, surrounded by the gate as depicted in Figure 2.2.…”

Section: Transistor Model and Scalingmentioning

confidence: 99%

See 1 more Smart Citation

3-D-DATE: A Circuit-Level Three-Dimensional DRAM Area, Timing, and Energy Model

Park

Davis

Franzon

2019

IEEE Trans. Circuits Syst. I

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Three-dimensional stacked DRAM technology has emerged recently. Many studies have shown that 3D DRAM is most promising solutions for future memory architecture to fulfill high bandwidth and high-speed operation with low energy consumption. It is necessary to explore 3D DRAM design space and find the optimum DRAM architecture in different system needs. However, a few studies have offered models for power and access latency calculations of DRAM designs in limited ranges. This has led to a growing gap in knowledge of the area, timing, and energy modeling of 3D DRAMs for utilization in the design process of processor architectures that could benefit from 3D DRAMs. This paper presents a circuit level DRAM Area, Timing, and Energy model (DATE) which supports 3D DRAM design with TSV. DATE provides front-end and back-end DRAM process roadmap from 90 nm to 16 nm node and provides a broader range 3D DRAM design model along with emerging transistor device. DATE is successfully validated against several commodity planar and 3D DRAMs and published prototype DRAMs with emerging device. Energy verification has a mean error of about -5% to 1%, with a standard deviation of up to 9.8%. Speed verification has a mean error of about -13% to -27% and a standard deviation of up to 24%. In the case of the area, the bank has a mean error of -3% and the whole die has a mean error of -1%. The standard deviation for area is up to 4.2%. In the case study, we demonstrate that 1Gb DDR3 DRAM designs achieve up to about 0.7 Gb/sec data throughput and energy efficiency of 510 bit/nJ using 3D design options with 16 nm DRAM technology.

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“…To reduce the cell size, vertical transistors are proposed for the DRAM cell transistor [10]. By using the vertical transistor for the memory cell transistor, both DRAM and SPRAM can realize a cell with an area of 4-F 2 , as shown in Fig.…”

Section: Scalable Cell Structure For High Density Sprammentioning

confidence: 99%